Effect of post metallization annealing on structural and electrical properties of Ge metal-oxide-semiconductor (MOS) capacitors with Pt/HfO 2 gate stack S.V. Jagadeesh Chandra a , Jin-Sung Kim b , Kyung-Won Moon b , Chel-Jong Choi a,b,⇑ a School of Semiconductor and Chemical Engineering, Semiconductor Physics Research Center (SPRC), Chonbuk National University, Jeonju 561-756, Republic of Korea b Department of BIN Fusion Technology, Chonbuk National University, Jeonju 561-756, Republic of Korea article info Article history: Available online 6 April 2011 Keywords: MOS HfO 2 Metal gate Effective work function EOT Fermi level pinning abstract We fabricated Ge metal-oxide-semiconductor (MOS) capacitors with Pt/HfO 2 gate stack and demon- strated the effects of post metallization annealing on their structural and electrical properties. Post met- allization annealing was carried out at the temperatures of 500 and 600 °C for 30 min in oxygen (O 2 ) ambient. Post metallization annealing at both temperatures led to the reduction of the interface traps density (D it ) with a decrease in accumulation capacitance. By considering the presence of interfacial layer (IL) in-between HfO 2 and Ge, the effective work function (U m,eff ) values of Pt gate electrode after anneal- ing at 500 and 600 °C, extracted from the relations of equivalent oxide thickness (EOT) versus flatband voltages (V FB ), were determined to be 4.05 and 5.43 eV, respectively. The presence of positive charge at the interface between HfO 2 and IL produced by the formation of oxygen-rich HfO 2 /IL interface resulted in the minimization of Fermi level pinning in Ge, which could be responsible for relatively high U m,eff value of Pt gate electrode in Ge MOS capacitor with O 2 post metallization annealing at 600 °C. Ó 2011 Elsevier B.V. All rights reserved. 1. Introduction There have been extensive studies on high dielectric constant (high-k) materials as a possible replacement for conventional SiO 2 gate dielectric in metal-oxide-semiconductor field-effect tran- sistors (MOSFETs), which require equivalent oxide thickness (EOT) less than 1 nm for 32 nm node and beyond. Among various high-k materials, HfO 2 has been identified as promising candidates to meet the scaling requirements stated in the International Technol- ogy Roadmap for Semiconductors [1]. In order to realize high de- vice performance, there is an ever-increasing need for alternate channel material to enhance the channel mobility beyond the physical limits of Si-based complementary metal-oxide-semicon- ductor (CMOS) devices without sacrificing the productivity required by semiconductor device manufacturers. Recently, Ge- channel MOSFETs have been received a lot of attentions due to the higher mobility of both the holes and the electrons in Ge rela- tive to Si [2]. Furthermore, narrower band-gap of Ge than that of Si facilitates the supply voltage scaling [3]. For further improvement in the operation performance of Ge-channel MOSFETs, the imple- mentation of metal gate electrode and high-k gate dielectric is re- quired. However, it suffers from the Fermi level pinning (FLP), which causes difficulty in controlling the effective work function (U m,eff ) of gate materials. Until now, many models have been pro- posed to explain the FLP of metal gate electrodes on several inter- faces. Among them, metal induced gap states (MIGS) model proposes an intrinsic component to FLP. Recently, it was reported that FLP in a metal-oxide-semiconductor (MOS) device could be associated with the intrinsic behavior of semiconductor material [4]. For instance, heavily doped p-type Ge substrate exhibits strong FLP around its charge neutrality level (CNL) [5] due to the intrinsic nature of Ge. It was shown that oxygen (O 2 ) annealing at around 500 °C is effective in the reduction of the FLP at Pt/HfO 2 interface deposited on Si substrate by modifying the proportion of ex- changed charge [6]. Houssa et al., [7] observed the reduction or compensation of negative fixed charge in ZrO 2 /Si stack by increas- ing O 2 annealing from 500 to 700 °C. Consequently, some other researchers noticed the production of positive charge in HfO 2 /Si stack with post metallization O 2 annealing in a range 600–800 °C [8]. Therefore, the existed negative charge in a high-k material could be compensated or reduced by the high temperature anneal- ing in O 2 ambient. Very recently, Jagadeesh Chandra et al. [9] re- ported the abnormally low value of U m,eff of Pt gate electrode in Ge MOS devices with HfO 2 gate dielectric. They also showed the presence of dipole density between HfO 2 and Ge caused by the non-uniform distribution of interface states on Ge surface. In this work, we focused on the O 2 annealing dependency of dipoles formed at the interface between HfO 2 gate dielectric and Ge substrate. 0167-9317/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.03.156 ⇑ Corresponding author at: School of Semiconductor and Chemical Engineering, Semiconductor Physics Research Center (SPRC), Chonbuk National University, Jeonju 561-756, Republic of Korea. E-mail address: cjchoi@chonbuk.ac.kr (C.-J. Choi). Microelectronic Engineering 89 (2012) 76–79 Contents lists available at ScienceDirect Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee