GaAs DGMESFET Modeling Using SGMESFET Models Saeed Bashirzadeh, Iran Telecommunication Research Center, Tehran, Iran bashir@itrc.ac.ir Abdolreza Nabavi Electrical Engineering Department Tarbiat Modarres University Tehran, Iran abdoln@modares.ac.ir Masoum Fardis Iran Telecommunication Research Center, Tehran, Iran fardis@itrc.ac.ir Abstract — This paper presents a complete and enhanced model for dual-gate MESFETs (DGMESFETs) using a cascode connection of dual single-gate MESFETs (SGMESFET) embedded by a group of external parasitic elements. An enhanced bias and frequency-dependent SGMESFET model is employed for internal SGFET’s, which accounts for charge-conservation and thermal effects. The initial values of the model parameters are obtained by measurement of DC and S-parameters. The parameters are then optimized using SAS, MATLAB and HSPICE. The model is implemented in HSPICE and its accuracy in predicting the characteristics of a NE25139 transistor is tested by DC and AC analysis. Index Terms — Dual-Gate, MESFET, DGMESFET, Model. I. INTRODUCTION Dual-gate metal-semiconductor filed effect transistors (DGMESFET); mainly made of GaAs semiconductor, have widespread usage in radio frequency communication circuits [1-5]. DGMESFET is a four terminal device and this increases its complexity in modeling and parameter extraction. Therefore, models with simple parameter extraction routine may be very helpful for MIC and MMIC designers. The earlier models for DGMESFET [3, 4] do not propose any method for parameter extraction and measurement. The other models based on equivalent circuit method [5-9], physical phenomena modeling, [10], and numerical methods [11, 12] handle the above problem. However, the authors in [5] focus on small signal modeling and employ a very complex procedure for parameter values optimization. This model has been simplified in [6] by neglecting certain phenomena in the device. Also, the simplified model embedded by parasitic elements has been given in [7]. The model in [8] is an analytical expression of an equivalent circuit using Y and Z parameters. The equivalent circuit model in [9] accounts for physical and parasitic effects in the device, and incorporates Curtice Cubic equations [10] for channel current modeling. However, the equations of a simple PN-junction capacitance represent gate-drain and gate-source capacitances in each SGFET. These equations are not accurate enough to predict all phenomena in the device, e.g., self-heating and frequency dispersion in channel current. Although some other models of MESFET are more accurate in channel current prediction [11-13], also the gate-drain/source capacitances are treated as a metal- semiconductor junction. Fig. 1 Internal structure of a DGMESFET. The models based on physics of the device [15] lead to complex equations. When the interaction between the circuit's elements is important, the convergence of these models is hardly achieved. The numerical models [8, 16, 17] focus on extracting equations by fitting to device characteristics, and hence neglect the circuits’ law constraints and device internal phenomena. In this paper, we propose an enhanced equivalent circuit with nonlinear elements using DGMESFET structure in [9]. An enhanced formula for channel current prediction is used that takes into account self-heating and frequency dispersion [11, 14]. In addition, Schottky diode model is employed to represent gate-drain/source junction. This model carefully predicts the nonlinear performance of the devices, and requires a relatively lower CPU time compared to physical / numerical-based models. Although the emphasis in this paper is on small-signal model of the device and its bias dependency, it can be extended for large signal prediction as well.