IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 3, MARCH 2010 479 Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits Chandan Karfa, Student Member, IEEE, Dipankar Sarkar, and Chittaranjan Mandal Abstract —A formal verification method of the datapath and controller generation phase of a high-level synthesis (HLS) process is described in this paper. The goal is achieved in two steps. In the first step, the datapath interconnection and the con- troller finite state machine description generated by a high-level synthesis process are analyzed to obtain the register transfer- operations executed in the datapath for a given control assertion pattern in each control step. In the second step, an equivalence checking method is deployed to establish equivalence between the input and the output behaviors of this phase. A rewriting method has been developed for the first step. Unlike many other reported techniques, our method is capable of validating pipelined and multicycle operations, if any, spanning over several states. The correctness and complexity of the presented method have been treated formally. The method is implemented and integrated with an existing HLS tool, called structured architecture synthesis tool. The experimental results on several HLS benchmarks indicate the effectiveness of the presented method. Index Terms—Controller, datapath, equivalence checking, for- mal verification, FSM, FSMD models, high-level synthesis, reg- ister transfer level. I. Introduction High-level synthesis (HLS) is the process of translating a be- havioral description into a register transfer level (RTL) descrip- tion containing a datapath and a controller [9]. The synthesis process consists of several subtasks carried out in sequence such as, scheduling, allocation and binding, and datapath and controller generation [9]. The operations in the behavioral description are assigned time steps in the scheduling phase. The allocation and binding process binds the variables to a set of registers and the operations to a set of functional units (FUs) in each control step. In the phase of datapath and controller generation, the first task is to generate the datapath by provid- ing a proper interconnection path from the source register(s) to the destination register for every register transfer (RT)- operation. The objective of this step is to maximize sharing of interconnection units among RT-operations ensuring conflict- Manuscript received January 14, 2009; revised July 2, 2009. Current version published February 24, 2010. This work was supported by Microsoft Corporation and Microsoft Research India under Microsoft Research India Ph.D. Fellowship Award, and in part by the Ministry of Communica- tions and Information Technology (SMDP-II projet), Government of India and the Department of Science and Technology, New Delhi, India, Grant SR/S3/EECE/053/2008. This paper was recommended by Associate Editor V. Bertacco. The authors are with the Department of Computer Science and Engi- neering, Indian Institute of Technology, Kharagpur 721302, India (e-mail: ckarfa@yahoo.co.in; ds@cse.iitkgp.ernet.in; chitta@iitkgp.ac.in). Digital Object Identifier 10.1109/TCAD.2009.2035542 free data transfers among the concurrent RT-operations. The second task is to generate the controller finite state machine (FSM) by identifying the control signals required in each state. Such a synthesis flow is depicted in Fig. 1. The use of high-level synthesis systems becomes crucial to deal with the increasing complexity of today’s very-large-scale integration designs and shortened design cycle. Continuous evolution in the HLS process, however, has made the synthesis steps so intricate that the synthesis procedures cannot be assumed to be correct by construction. Designs synthesized by HLS may contain errors due to bugs in the tool. For instance, the research reported in [18] identified two bugs in a widely used HLS tool SPARK [10] recently. We have an indigenous synthesis tool structured architecture synthesis tool (SAST) in which flaws resulting from bugs in the tool have been uncovered in the course of formally verifying its output. This underlines the need for efficient verification mechanisms for HLS. The research reported in [7], [8], [19], [23] tried to formally establish end-to-end equivalence between the input behavioral description and the design synthesized by HLS. However, the input specification of HLS is given at a high abstraction level compared to the level of abstraction of the output. Also, extensive optimizations are carried out at various phases. An end-to-end verification technique falls short of meeting all the challenges posed by phase-specific verification tasks. The above techniques have to make some simplifying assumptions regarding the synthesis flow. In [19], for example, it is assumed that code motion techniques [11] have not been applied during scheduling which, however, is quite contrary to what happens in most of the modern day HLS tools such as SPARK [10]. Therefore, a phase-wise verification technique that can handle the difficulties of each synthesis subtask separately is desirable for HLS verification. A verification flow which works hand-in-hand with HLS is depicted in Fig. 1. A number of researches were reported in the literature on verification of each phase of HLS. Verification of the phase of scheduling is addressed in [5], [6], [14], [16]–[18], [21], that of allocation and binding in [15], [20], and that of datapath and controller generation in [1], [3]. The objective of this paper is to ensure the correctness of the datapath and controller generation phase assuming that the scheduling phase and the allocation and binding phase have already been verified. Although this phase does not bring about any change in the control flow, the verification of this phase still has many challenges. First and foremost, the input RTL behavior transforms to an output consisting of 0278-0070/$26.00 c  2010 IEEE www.DownloadPaper.ir www.DownloadPaper.ir