Negative Bias Temperature Instability of Bulk Fin Field Effect Transistor Sang-Yun KIM, Kyoung-Rok HAN, Byung-Kil CHOI, Seong-Ho KONG, Jae-Sung LEE 1 and Jong-Ho LEE School of Electronic and Electrical Engineering, Kyungpook National University, Bldg. #11-503, 1370 Sankyuk-Dong, Buk-Gu, Daegu 702-701, Korea 1 Division of Information and Communication Engineering, Uiduk University, San 50, Gyongju 780-713, Korea (Received September 2, 2005; revised November 9, 2005; accepted December 4, 2005; published online March 8, 2006) We investigated the negative bias temperature instability (NBTI) of bulk fin field effect transistor (FinFET) for the first time. Because bulk FinFET has a body terminal, it is more flexible in studying NBTI characteristics than a silicon on insulator (SOI) FinFET (no body terminal). The dependence of NBTI on back bias is smaller in 100 nm bulk FinFET with a fin width of 30 nm than in conventional planar channel devices. The bulk FinFET with the side surface orientation of (100) showed better NBTI than the device with the orientation of (110). The fin width variation has little impact on the NBTI of bulk FinFET. Moreover, the device with longer channel showed less degradation. [DOI: 10.1143/JJAP.45.1467] KEYWORDS: negative bias temperature instability, NBTI, bulk FinFET, back bias 1. Introduction As device size is continuously scaled down, novel device structures are needed to suppress the so-called short-channel effect (SCE). Bulk fin field effect transistor (FinFETs) which are built on bulk Si wafer have been reported as one of the promising candidates 1–3) for future complementary metal– oxide semiconductor (CMOS) technology. Bulk FinFETs have the same scalability as that of silicon on insulator (SOI) FinFETs, 4) and provide lower wafer cost, lower defect density, and higher heat transfer rate than SOI FinFETs. Additional advantages over conventional MOS devices are better scalability and less back bias effect. 3) In those scaled FinFETs and double/triple-gate metal–oxide semiconductor field effect transistors (MOSFET), the NBTI of p-type MOS (PMOS) devices is one of the serious problems, 5) because negative bias temperature instability (NBTI) shifts threshold voltage and degrades the device lifetime. Both interface-trap state and oxide-fixed charge are changed during NBTI stress, which causes threshold voltage shift. The degradation due to NBTI is more severe in p þ gate PMOSFET than in n-type MOSFET (NMOSFET). The NBTI of triple-gate PMOS device built on SOI wafer was previously characterized. 6) However, the SOI triple-gate device in ref. 6 has no body terminal, so that we were not able to observe body current which shows the extent of impact ionization and we were not able to apply any body bias as a manner of stress measure- ment. In this study, we characterize the NBTI of bulk FinFETs for the first time. The body of the bulk FinFET is connected directly to the substrate, so that we can utilize the body terminal during measurement. We show the NBTI character- istics with body bias, and its dependence on crystal orientation, temperature, fin body width, and channel length. 2. Device Structure and I–V Charcateristic Figure 1 shows the schematic three-dimensional (3-D) view of the bulk FinFET. In the bulk FinFET, current flows on the top surface and both side surfaces of the fin body wrapped around by a gate electrode as shown in the insert of Fig. 1. The fin body is directly connected to the substrate. Because the body in double/triple-gate devices based on SOI wafers is floated, the NBTI may be different to some extent from that of our bulk FinFET. The gate oxide thicknesses of the bulk FinFET are 1.8 nm on the top surface and 5.5 nm on the side surfaces of the fin body, respectively. The p þ polycrystalline silicon (poly-Si) gate was applied to p-type bulk FinFET. The fin height (H g ) is the height of the side channel formed on one of the side surfaces of the fin body. The height is approximately 85 nm. The total dielec- tric thickness in shallow trench isolation (STI) is approx- imately 350 nm. W fin is the fin body width. We measured threshold voltage shift in bulk FinFETs with NBTI. The minus voltage was applied to the gate of the bulk FinFET while source, drain, and substrate electrodes are grounded. The current–voltage (I –V ) data are shown in Fig. 2. For gate bias higher than approximately 1:5 V, the substrate current which can be identified with electron current rapidly increases. To avoid the impact ionization effect due to the electron current, the gate bias of 2 V is selected as a reasonable stressing condition for our bulk FinFET. 3. NBTI Results and Discussion Figure 3 shows the threshold voltage shift (V th ) of bulk FinFET (W fin ¼ 30 nm and L g ¼ 100 nm) along with those of conventional planar MOSFETs with W=L of 10/0.15 um. Fig. 1. Three-dimensional schematic view of bulk FinFET for NBTI measurement. Japanese Journal of Applied Physics Vol. 45, No. 3A, 2006, pp. 1467–1470 #2006 The Japan Society of Applied Physics 1467