Fully Depleted Double-Gate 1T-DRAM Cell with NVM Function for High Performance and High Density Embedded DRAM Ki-Heung Park, Young Min Kim, Hyuck-In Kwon*, Seong Ho Kong, and Jong-Ho Lee School of EECS, Kyungpook National University 1370 Sankyuk-Dong, Buk-Gu, Daegu, 702-701 Korea *School of Electronic Engineering, Daegu University, Jillyang, Gyeongsan, Gyeongbuk, 712-714 Korea Phone: +82-53-950-6561 E-mail: jongho@ee.knu.ac.kr 1. Introduction Partially depleted (PD) SOI MOSFETs have been used for 1T-DRAM cells thanks to high charge capacity of the floating body. However, these devices have poor scalability in deep sub-100 nm due to short-channel effects (SCE) [1]-[3]. To improve the scalability of 1T-DRAM DRAM cells, in general the body impurity concentration increases and the silicon thickness decreases. As a result, the retention time becomes shorter due to the increasing junction leakage current and reduced body charge capacity. As a solution of these problems, we have reported fully depleted (FD) double-gate (DG) 1-T DRAM cells which have SONOS type storage node on the bottom control gate (CG) for nonvolatile memory (NVM) function [4]. Enlarged hole capacity in the floating body by the NVM function was useful in enhancing performance. However, long CG length and deep source/drain junction depth give poor retention characteristics of the cell due to GIDL under the overlapped region between the drain and the CG. In this work, we propose a FD DG 1T-DRAM cell to solve GIDL problem, and investigate the device characteristics. We also show the scalability of proposed device by using 3-D device simulator [5]. The DG 1T-DRAM cells with the NVM function are fabricated and measured device characteristics are shown. 2. Cell Operation and Device Fabrication Fig. 1 shows 2-D schematic view of proposed device structure. The n + and p + poly-Si gates were applied to the top gate (TG) and CG, respectively. The L cg represents CG length. The x j in the figure stands for the S/D junction depth defined from the bottom of the gate oxide. Key point in this structure is that the x j should not be touched to the back interface. The overlap length between the S/D and top gate is fixed at 0 nm. The T si stands for silicon body thickness. The top gate oxide thickness (T ox ) is fixed at 5 nm. The uniform body doping is 1×10 18 cm -3 . The thickness of O/N/O layers is 3/5/6 nm. The S/D doping concentration is 1×10 20 cm -3 . Heavily doped S/D is elevated by selective epi growth (SEG). The CG is used to charge or discharge the nitride storage node. By applying positive CG bias, electrons are trapped in the nitride layer. The electrons results in hole accumulation in the body, which increases V th . Electrons can be injected into the storage node by Fowler-Nordheim (FN) tunneling. Although T si in proposed device is thin to operate in FD mode, we can achieve PD operation by trapping electrons in the storage node. For write “1” operation, impact ionization (II) mechanism is used to store holes in the body. For write “0” operation, the body-drain junction is forward-biased, resulting in hole deficiency in the body. The operation conditions are summarized in Table I. Fig. 2 represents cross-sectional TEM view of fabricated DG device. 3. Results and Discussion Figs. 3 to 4 show device characteristics of fabricated DG device as a parameter of CG bias (V cg ). Differently from the device structure shown in Fig. 1, fabricated devices have a uniform body thickness of 70 nm. The W and L g of the devices are 0.6 μm. After write “1”, the I s increases because of accumulated holes in the floating body and the resultant V th decrease. As V cg increases, the sensing margin increases significantly. When the V cg is -5 V, I s under the write “0” state increases with time since the holes by GIDL generation in the drain overlapped by the CG supply to depleted floating body. The retention characteristic at the V cg of 0 V is very poor. As the V cg decreases from 0 V to -1.5 V, sensing margin is improved significantly. After 100 ms, the I s at V cg = -1.5 V was measured from ~ 4 μA (“0” state) to 4.6 μA (“1” state). When comparing the decreasing slopes of retention characteristics in 0.5 ms shown in Fig. 4, negatively increasing V cg gives steeper slope, which means smaller excess hole capacity during write “1”. However, write “0” state is improved dominantly, resulting in the improved sensing margin. Fig. 5 shows transient I s characteristics of fabricated DG device as a parameter of the programmed charge (Q). After FN program, sensing margin in I s is improved from ~ 0.8 μA to ~1.5 μA. In the following figures, we check simulated characteristics by changing x j in FD devices with an elevated S/D as shown in Fig. 1. Fig. 6 shows transient I s characteristics of DG device with a T si of 30 nm in the channel as a parameter of x j . As the x j changes from 30 nm to 5 nm, I s (write“1”) /I s (write“0”) ratio of the device increases from 2 to 9.7 due to improved “0” state characteristics. Fig. 7 shows the retention characteristics with the x j under the read condition. As the x j changes from 30 nm to 5 nm, we can also observe improving retention characteristics due to significantly reduced GIDL. For the x j s deeper than ~20 nm, the retention characteristic is very poor. For the given geometry, we could obtain an optimum x j range of < ~15 nm. Fig. 8 shows the retention characteristics with the L cg under the read condition. The x j is fixed at 15 nm. As the L cg increases from 50 nm to 300 nm, they show excellent retention characteristics even after 200 ms. At even 100 ms, the I s (=I s (write“1”)-I s (write“0”)) for L cg = 300 nm is ~4.8 μA and the I s ratio is larger than 2. This is explained by a large excess hole capacity in the floating body due to electrons stored in long storage node. Thus longer L cg gives larger I s without degrading cell scalability by utilizing the space under the body. Fig. 9 shows transient I s characteristics of FD DG device with the L g . The x j is fixed at 15 nm. As the L g decreases, the I s ratio decreases. The I s ratio of 50 nm device is larger than 2.5 for a given thin T si . Fig. 10 shows the retention characteristics with the L g under the read condition. At L g s of 50 nm and 80 nm, I s ratio are 1.4 and 1.9 at 200 ms, respectively. Decreasing L g increases degradation rate under write “0” state. To verify the effect of Q in the storage node, retention characteristics were checked for several Qs, as shown in Fig. 11. The write “1” state is negligibly affected by Q change. For the Qs less than ~1.7×10 12 cm -2 , the I s is almost 0 at ~tens ms. As the stored charge density increases, the I s is improved and is saturated for further increase of Q more than ~2.7×10 13 cm -2 . 4. Conclusion We have investigated a fully depleted double-gate 1-T DRAM cell device which has SONOS type storage node on control gate for nonvolatile memory function. Due to enlarged hole capacity by the large storage node and source/drain junction depth control in the floating body, we could improving data retention time, I s (write“1”)/I s (write“0”) and device scalability. Proposed device could be a very promising candidate for a future high density and high performance 1T-DRAM cell. Acknowledgements This work was supported by “SystemIC 2010 Project” in 2008 978-1-4244-3761-0/09/$25.00 ©2009 IEEE 32