Variation study of process parameters in Trigate SOI-FinFET D. Singh, S. K. Mohapatra, K. P. Pradhan, P. K. Sahu Department of Electrical Engineering, National Institute of Technology (NIT), Rourkela, 769008, Odisha India. erdevendersingh@gmail.com , s.k.mohapatra@ieee.org, kp2.etc@gmail.com , pksahu@nitrkl.ac.in . Abstract— This work presents the simulation of quantum transport in tri-gate (TG) silicon-on-insulator (SOI) FinFET using 3-D numerical simulation. The impact of process parameters like fin height (H Fin ), fin width (W Fin ), length of underlap (L un ) in both source and drain side are investigated using Sentaurus device simulator. The effectiveness and optimization of the process parameters required in SOI FinFETs to enable them catch up with the DC performance are systematically investigated. The performances such as threshold voltage (V th ), on current (I on ), off current (I off ), transconductance (g m ) and transconductance generation factor (TGF=g m /I D ) of FinFET are analyzed. The results show for H Fin /L g =0.8 and W Fin /L g =0.6 have higher I on and lower I off which is more suitable for circuit applications. Keywords— Tri-Gate, SOI-FinFET, Device geometry, Process parameters variability. I. INTRODUCTION To satisfy the market demand, the density of transistors in a chip and the performance in terms of speed and power consumption are need to increase. The transistor miniaturization is one of the major concern behind the performance and cost. Undesirable short channel effects (SCEs) and excessive V th variation occurred beyond 32 nm technology node [1][2]. However the Integrated Device Manufacturer (IDM), foundries and electronic design automation (EDA) companies give more investments and emphasis on most promising 3-D FinFET technology. The advantages of FinFET technology are higher drain current and switching speed, less than half the dynamic power requirement with 90% less static leakage current [3][4]. The most important geometric parameters of a FinFET are its fin height (H Fin ), fin width (W Fin ), and gate length (L g ) as shown in Fig. 1 [5]. A trade–off required between drive current with H Fin and W Fin [6][7]. The complete work in this paper is organized as follow: Section II shows the device architecture of Tri-Gate (TG) SOI FinFET with different cases considered for this work. Section III describes about the calibration of simulation procedure using the device simulator Sentaurus TM [5]. In section IV, the investigation is made for optimization of the device dimensions on various process parameters. Finally the conclusions are drawn in section V. II. FINFET DESIGN Table I shows the design considerations of a 3-D n-channel TG-SOI-FinFET with high-k material (Si 3 N 4 ) as spacer in the underlap regions for simulation. TABLE I. TYPICAL CASES OF 3D SOI FINEET FOR SIMULATION Device Design Lg in nm HFin/Lg WFin/Lg Lun/Lg 20 1 0.5 0.25 10, 30, 40 1 0.5 0.25 20 0.25, 0.6, 0.8, 1.1, 1.3 0.5 0.25 20 1 0.25, 0.6, 0.8 0.25 20 1 0.5 0.125, 0.2, 0.5 Fig. 1. Perspective view of SOI FinFET (a) 3-D view (b) 2-D view in x-y (c) 2-D view in y-z . The metal and spacer regions are made trasparent in (a) Fig. 1 shows the different view of the TG-MOSFETs with Source/Drain length (L S /L D ) as 40 nm. The source drain doping is uniform with N D at a density of 10 20 cm -3 . The Equivalent Oxide Thickness (EOT) is 0.9 nm [8][9] and supply voltage V DD = 0.7 V. The work function for the gate electrode is assumed as 4.5 eV. The channel is lightly doped (10 15 cm -3 ) 978-1-4799-5364-6/14/$31.00 ©2014 IEEE 2014 Annual IEEE India Conference (INDICON)