119 Original scientific paper  MIDEM Society Impact of Downscaling on Analog/RF Performance of sub-100nm GS-DG MOSFET P. K. Sahu, S. K. Mohapatra, K. P. Pradhan Nano Electronics Laboratory, Department of Electrical Engineering, National Institute of Technology (NIT), Rourkela, Odisha, India Abstract: This paper presents a systematic study to show the impact of channel length on the Analog/RF performances of gate stack (GS) silicon on insulator (SOI) architecture. The downscaling of channel length becomes the biggest challenge to maintain higher speed, low power and better electrostatic integrity for each generation. This investigation is done to find out the potential of the channel length in view of analog and RF performance measures of sub-100nm GS-double gate (DG) MOSFETs. The threshold voltage (V th ) is made constant by tuning the gate metal work function while downscale the channel length (L). The impact of channel length variation on subthreshold slope (SS), drain induced barrier lowering (DIBL), transconductance (g m ), output conductance (g d ), early voltage (V EA ), transconductance generation factor (TGF), intrinsic gain (A V ), cut-off frequency (f T ), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) are rigorously examined. It is shown that gate stack design results in higher cut-off frequency along with a broader analog ‘sweet spot’ in nanoscale MOSFETs thus offering better possibilities for analog/RF scaling below 50nm. For shorter gate length devices (L=30nm), the design results in an impressive 69.10% improvement in f T along with 36.31% enhancement in ‘sweet spot’ as compared to L=60 nm. The study generates an optimized channel length of L=40 nm for the designed device dimension in connection with the analog and RF performance for circuit design. Keywords: Gate Stack (GS), DG-MOSFETs, Metal Gate Technology, Analog/RF FOMs, Sweet Spot Vpliva pomanjševanja na analogne/RF lastnosti pod-100 nm GS-DG MOSFETa Izvleček: V članku je predstavljana sistematična študija vpliva dolžine kanala na analogne RF lastnosti arhitekture večplastnih vrat (GS) silicija na izolatorju (SOI). Največji izziv pri krajšanju kanala je ohranjanje visoke hitrosti, nizke moči in boljše elektrostatične celote. Raziskava odkriva potenciale dolžine kanala pri analognih in RF lastnostih. MOSFET-ov z dvojnimi vrati. Konstantnost pragovne napetosti pri krajšanju kanala se je ohranjala s spreminjanjem delovne funkcije kovinskih vrat. Raziskan je vpliv krajšanja kanala na podpragovni naklon (SS), ponorno vzbujano nižanje bariere, transkonduktanco (g m ), izhodno prevodnost (g d ), zgodnjo napetost (V EA ), generacijski faktor transkonduktance (TGF), intrinsično ojačenje (A V ), frekvenco reza (f T ), produkt transconduktančne frekvence (TFP), produkt frekvence ojačenja (GFP) in produkt frekvenc ojačenja in transkonduktance (GTFP). Izkazalo se je, da večplastna vrata omogočajo višje frekvence reza skupaj s širšim območjem najboljšega delovanja v nanodimenzijskih MOSFET-ih, kar omogoča krčenje na 50 nm. Pri krajših dolžinah vrat (L=30nm) oblika izkazuje impresivno 69.10 % izboljšanje f T in 36.31 % izboljšanje območja najboljšega izplena v primerjavi z L = 60 nm. Izkazalo se je, da je optimalna dolžina kanala 40 nm. Ključne besede: večplastna vrata, DG-MOSFET, tehnologija kovinskih vrat, Analogni/RF FOM, območje najboljšega izplena * Corresponding Author’s e-mail: kp2.etc@gmail.com Journal of Microelectronics, Electronic Components and Materials Vol. 44, No. 2 (2014), 119 – 125 1 Introduction The use of low power and high frequency operated de- vices are having a high priority for future electronic ap- plications. Silicon on Insulator (SOI) devices are excel- lent candidates as an alternative for the conventional bulk CMOS [1-2]. Advanced MOSFET structures such as ultra-thin body (UTB) SOI double gate (DG) MOSFET can be scaled more aggressively than bulk Si structure [3]. A double gate structure fabricated on SOI wafer has been utilized in CMOS technology due to their ex- cellent scaling capability, outstanding Short Channel Effects (SCEs) immunity, high current drivability (I on ) and transconductance (g m ) and lower leakage current (I off ) as compared to the bulk MOSFETs [4-10]. Channel length scaling is limited by the ability to control off-