International Journal of Computer Applications (0975 – 8887) Volume 66– No.7, March 2013 12 Evolutionary Algorithms for Low Power Test Pattern Generator Bagavathi Chandrasekara Assistant Professor Department of Electronics and Communication Engineering K.S.R. College of Engineering Tiruchengode – 637 215 ABSTRACT VLSI testing has been an essential part of chip design recently. A circuit must be tested before fabricating to avoid any malfunctioning. Testing a circuit has become mandatory that the circuit must be designed by ensuring testability. In VLSI testing, the circuit for testing is embedded with the actual design itself to reduce area and it is known to be Built- In Self Test (BIST). The test patterns generated by BIST are applied to the circuit. The test patterns are to be optimized to cover all the faults, reduce testing time and consume less power. This is achieved by employing Evolutionary Algorithms in selecting the patterns such that the inputs of design switch minimally. Test pattern generator is designed using these evolutionary algorithms so that the test vectors selected can be used for reducing the switching activity in the circuit and also by maintain the fault coverage. Genetic Algorithm and Particle Swarm Optimization are concentrated and their efficiencies are explained in this work General Terms VLSI Testing, Evolutionary Algorithms Keywords Evolutionary algorithms, Genetic Algorithm, Particle Swarm optimization, Low power, Test Pattern Generation. 1. INTRODUCTION With the increasing use of portable computing and wireless communications, power dissipation has been a major concern in today’s VLSI systems. A circuit or system consumes more power in test mode than in normal mode. It has been reported that power consumption of VLSI chip during test application can be as high as 200% of that in normal mode [1]. This extra power consumption can give rise to severe threats for circuit reliability and can even inflame instant circuit damage. Moreover, it can fashion complications such as amplified product cost, striving in performance verification, reduced autonomy of portable systems, and decline of overall yield [2]. Low power dissipation during test application is becoming progressively more imperative in today’s VLSI systems design and is a major goal in the future development of VLSI design [1]. One handy method to reduce power dissipation during testing is to reduce the circuit transition between successive test inputs by choosing weighted random patterns [3] and transition density patterns [4]. BIST design is the most recurrently used technique for testing a chip for its well-known advantages. Since BIST is an in- built testing mechanism, the power consumption of BIST has to be reduced [5]. The BIST architecture consists of a linear feedback shift register (LFSR), a clock and circular shift register. The power consumed is mainly in the test patterns generated by LFSR as they are rarely correlated [6]. But in normal mode of a circuit operation, the patterns applied as input are highly allied. For testing procedure, highly uncorrelated patterns can be avoided so that the power consumed during testing can be reduced and the test pattern set can be compacted [7]. The parameters to be considered are fault coverage and weighted switching activity for low power BIST [8]. These indiscriminate test inputs are to be selected through evolutionary processes which have proved good in VLSI testing [9]. Evolutionary algorithms are well known for their robustness and self-adaptation [10]. These algorithms are extensively used in many applications such as VLSI testing, physical design and many more fields which require coordinated, controlled way of randomness inserted in the process of finding the solution. Genetic Algorithm and Particle Swarm Optimization are the two techniques that are to be focused in this paper for Test pattern generation with main emphasis on low power dissipation. 2. BUILT-IN SELF TEST Built-in Self Test is a design procedure in which elements of a circuit are used to test the circuit itself [6]. It is the potential of a circuit to test itself. In circuit testing, the circuit can be tested using all possible combinations of input vectors or only the necessary vectors that can find the faults exactly. Sometimes a single vector can spot more than one faults. Whenever a set of test vectors are applied to a circuit sequentially, there will be a lot of switching in the inputs and outputs. To reduce the power during testing, minimum switching must be ensured. Hence, instead of using exhaustive testing, test vector size compaction can be used to reduce the memory requirements of BIST architecture. The inputs can be grouped in such a manner that there is reduction in space needs. The main component of BIST is Linear Feedback Shift Register (LFSR) [11]. LFSR contains a sequence of registers or D-flip flop which is independent or guarded by clock. The circuit is cyclic in the sense that when clocked repeatedly, they result in a fixed sequence of states. Consider a LFSR with n flip-flops, it goes through 2n states. The last state can be just fed back to the first stage or it can be given to a modulo-2 adder, whose another input is state of any flip-flop other than last flip-flop. A cyclic shift register is used to shift and produce 2n patterns for n inputs.