CHARACTERIZATION OF THRESHOLD VOLTAGE INSTABILITY AFTER PROGRAM IN CHARGE TRAP FLASH MEMORY Bio KIM, SeungJae BAIK, Sunjung KIM, Joon-Gon LEE, Bonyoung KOO, Siyoung CHOI, Joo-Tae MOON Process Development Team Memory R&D Center, Samsung Electronics Co., Ltd. l San #16 Banwol-Dong, Hwasung-City, Gyeonggi-Do, Korea phone: +82-31-208-2988, e-mail: bioman.kim@samsung.com Abstract— We investigated threshold voltage shifts after program pulse in charge trap flash memory by measuring drain current changes. We have found threshold voltage shifts can be characterized as a function of not only the materials of tunnel oxide, trap layer, blocking layer, but also physical parameters like device size and electrical measurement environment such as program voltage target and gate bias voltage. This approach can identify the root cause of initial threshold voltage shifts in charge trap flash memory devices. Keywords-component; Charge Trap flash, Threshold voltage shift, electron detrapping, lateral spreading I. INTRODUCTION To increase the density of flash memory cell, multi-level program cell (MLC) technique is widely used. The MLC NAND flash memory has two or three times higher density of single-level program cell. Precise control of threshold voltage (Vth) of NAND flash is essential for MLC application and it can be achieved by using incremental step pulse programming (ISPP) schemes. ISPP is an effective method to adjust Vth, because the Vth of a cell generally follows the ISPP step pulse voltage [1]. This ISPP scheme is also adopted to charge trap flash (CTF) memory, one of the candidates to solve the scaling problems of floating-gate devices [2]. The Vth distribution of the cells programmed by ISPP method in CTF memory is shown in Figure 1. Ideally, we can expect the width of Vth distribution is smaller than ISPP voltage step and the lower tail of Vth is larger than ISPP verify level. However, the actual distribution becomes broader than expected [3] and the lower tail value of Vth is smaller than the verification level by 0.1 V ~ 0.3 V. Since the Vth distribution should be narrower than 1 V for MLC flash memory, Vth shift after ISPP program process should be kept as small as possible, otherwise it may lead to wrong data reading. Long term measurement after program pulse shows that charge detrapping from tunnel oxide can cause Vth instability and induce retention fails [4,5]. However, the Vth shift in short term, less than 10 sec, to verify Vth distribution shift is not measured and the reason of short term Vth shift is not known yet. In this paper, for the first time we clarified Vth shift behavior in CTF NAND flash cell array by measuring Vth shift of single transistor after program pulse. II. SAMPLE DESCRIPTION Typical CTF devices were fabricated in a single transistor (tr) structure. The basic structure is Metal-AlO-SiN-Oxide-Si (MANOS) structure and we changed the materials of blocking, trap, and tunnel layers to compare the effect of each layer to the Vth shift. And the transistors were fabricated with various channel width and length ranging from 0.064μm x 0.1μm to 100μm x 100μm to study the size dependences. The splits of stack structure evaluated in this experiment are shown in Table I. Six different stacks with different kinds of tunnel, trap, and blocking layers were prepared. The Oxide1, split into three thicknesses, has low trap density while Oixde2 has high trap density. Two different kinds of materials were also used for trap and blocking layers. Normal LPCVD SiN and high-k material with dielectric constant of 10~20 were used for trap layer. AlO and higher-k material which had 2~4 times higher dielectric constant than AlO were used for blocking materials. Vth number of bit ISPP voltage step Verify level Ideal Verify result Figure 1. Ideal Vth distribution and real Vth distribution after ISPP . Sample number Tunnel oxide Trap Blocking Quality Thickness 1 Oxide1 Thick SiN AlO 2 Middle 3 Thin 4 Oxide2 Thick 5 Oxide1 Thick high-k 6 SiN higher-k TABLE I. DEVICE SPLIT. TWO KINDS OF MATERIALS ARE USED FOT TUNNEL, TRAP AND BLOCKING LAYERS. OXIDE1 HAS LOW TRAP DENSITY AND OXIDE2 HAS HIGH TRAP DENSITY. ALO HAS LOW TRAP DENSITY AND HIGHER-K HAS HIGH TRAP DENSITY Physics Symposium, Montreal, 2009 IEEE CFP09RPS-CDR 47th Annual International Reliability 978-1-4244-2889-2/09/$25.00 ©2009 IEEE 284