Run-time reconfiguration for automatic hardware/software partitioning Tom Davidson ELIS department, Ghent University Sint-pietersnieuwstraat, 41 9000, Ghent, Belgium Email: tom.davidson@ugent.be Karel Bruneel ELIS department, Ghent University Sint-pietersnieuwstraat, 41 9000, Ghent, Belgium Email: karel.bruneel@ugent.be Dirk Stroobandt ELIS department, Ghent University Sint-pietersnieuwstraat, 41 9000, Ghent, Belgium Email: dirk.stroobandt@ugent.be Abstract—Parameterisable configurations allow very fast run- time reconfiguration in FPGAs. The main advantage of this new concept is the automated tool flow that converts a hardware design into a more resource-efficient run-time reconfigurable design without a large design effort. In this paper, we show that the automated tool flow for run-time reconfiguration can be used to easily optimize a full hardware implementation for area by converting it automatically to a hardware/software implementation. This tool flow can partition the design in a very short time and, at the same time, result in significant area gains. The usage of run time reconfiguration allows us to extend the hardware/software boundary so more functionality can be moved to software. We will explain the core principles behind the run-time reconfiguration technique using the AES encoder as an example. For the AES encoder the manual hardware/software partitioning is clear. This manual partitioning will serve as a comparison to the automated partitioning that uses parameterisable con- figurations. Several possible AES encoder implementations are compared. Our automatically partitioned AES design shows a 20.6 % area gain compared to an unoptimized hardware implementation and a 5.3 % gain compared to a manually optimized 3rd party hardware implementation. In addition, we discuss the results of our technique on other applications, where the hardware/software partitioning is less clear. Among these, a TripleDES implementation shows a 29.3 % area gain using our technique. Based on our AES encoder results, we derive some guidelines for optimizing the impact of parameterisable configurations in general designs. I. I NTRODUCTION Parameterisable configuration is a new concept for FPGA reconfiguration that was developed to allow for easier run-time reconfiguration (RTR) design [1]. This concept is implemented in the TMAP toolflow, an alternative to the normal FPGA tool flow. The TMAP tool flow allows us to automatically make a design run-time reconfigurable. It’s principles and advantages are discussed in Section II-A. Because this is a new technique, there is still a lot of exploration needed to fully understand how it should be used and what the potential gains are for different applications. This paper aims to fill part of this void, by showing how parameterisable configuration can be used for fast hardware/software partitioning. The TMAP tool flow allows us to very quickly transform a hardware implementation to a hardware/software implementation that is optimized for area. To explain how parameterisable configuration allows for an extended hardware/software partitioning, we use an application that is easy and clear to partition manually. One application that fits these needs is AES, Advanced Encryption Standard, an encryption algorithm detailed by the NIST in [2]. AES is explained in more detail in Section II-B. Next, in Section III, we will first detail the design decisions for our own AES im- plementation, k AES, and then explain how exactly the TMAP tool flow is used on this application for hardware/software partitioning. Here we will also discuss the advantages of this tool flow compared to a more traditional hardware/software partitioning that does not use run time reconfiguration. In Section IV we will discuss the result of applying TMAP to k AES. We show a 20.9 % area gain for the k AES implementation, compared to the normal FPGA tool flow. In addition we will compare this result with two other, manually optimized, designs, Cryptopan [3] and Avalon AES [4]. And lastly, we will also use TMAP on both manually optimized designs, and discuss these results. Section V shows that TMAP can attain similar gains in designs that are more difficult to partition manually. In Section V, we will also provide guide- lines for designing your implementation to take advantage of the concept of parameterisable configuration, and how to get a maximum gain out of the TMAP toolflow. II. BACKGROUND A. Parameterisable configurations and TMAP FPGAs can be configured to implement any function, as long as there are enough FPGA resources available. The functions on the FPGA are completely controlled by memory, this memory is called the configuration memory. An FPGA configuration of a design describes what values the configura- tion memory should have to implement the design. Since the configuration memory consists of SRAMs, this memory can be overwritten at run-time, which means that the functionality on an FPGA can be changed at run-time. This is why FPGAs can be used for run-time reconfigurable implementations of applications. Parameterisable configurations are a new concept for run- time reconfiguration on FPGAs. A parameterisable configura- tion is an FPGA configuration where some of the bits are expressed as boolean functions instead of boolean values.