Hierarchical Test Generation with Built-in Fault Diagnosis Dirk Stroobandt Jan Van Campenhout University of Ghent Department of Electronics and Information Systems St.-Pietersnieuwstraat 41, B-9000 Gent, Belgium dstr,jvc @elis.rug.ac.be Abstract A hierarchical test generation method is presented that uses the inherent hierarchical structure of the circuit under test and takes fault diagnosability into account right from the start. An efficient test compaction method leads to a very compact test set, while retaining a maximum of diagnostic power and a 100% fault coverage for non-fanout circuits. An extension for fanout circuits is also presented. 1 Introduction In the production of VLSI and ULSI components, testing takes considerable development time and effort. To reduce this effort, people have tried to make testing more efficient. The popular D-algorithm and its variations, PODEM,FAN, SOCRATES, and other algorithms emerged [7]. Nowadays, more and more VLSI-components have built-in testing fea- tures. Still, even more efficient and accurate testing strate- gies are badly needed. With the increased complexity of components, many re- searchers have felt the need to exploit the hierarchy in sys- tems architecture, producing separate tests for each module [1, 13, 14]. This way, the testing problem can be reduced considerably. In this paper, we present a method for auto- matic test pattern generation that uses the hierarchical nature of the components down to the gate-level. The test set itself is built hierarchically from tests for lower-level parts of the module. Our method also has the advantage that the test set ob- tained has excellent diagnostic capabilities. This means that, after applying the tests, one can immediately tell which parts of the module are defective. Unlike other diagnosis schemes (such as those using fault dictionaries [5], DIATEST [4] and others [2, 10, 18]), the extra tests needed for the diag- Supported as Research Assistant with the Belgian National Fund for Scientific Research. nosis are automatically added to the test set from the begin- ning. Yet, the test set with its diagnostic capabilities is kept very small due to an efficient compaction method [16, 17]. In the next section, the advantages of our method are highlighted and the improvements on the existing methods are pointed out. In sections 3, 4, and 5 the principles of the hierarchical test generation method and the compaction method are presented. Section 6 explains how the method can be expanded to also cover circuits with fanout lines. The results obtained can be found in section 7. 2 Hierarchical test generation and diagnosis Testing combinational circuits is not as difficult as testing sequential circuits. This is the reason why the well-known scan-path technique is used so often. All flip-flops are linked into one (or more) long shift register(s), called the scan-path, which can be tested independently of the rest of the circuit by applying a well-chosen bit stream. If this test succeeds, the flip-flop inputs can be considered as observable outputs of the combinational circuit and the flip-flop outputs can be used as controllable inputs. This way, the testing problem of sequential circuits equipped with a scan-path is reduced to a combinational one [19]. Our method can fully test and di- agnose combinational circuits or circuits designed with the scan-path technique. With the classical ATPG algorithms, tests are generated by propagating and back-tracing fault-effects throughout the circuit. The aim is to find a set of input values that make a certain fault observable at the primary outputs. Typically, the circuit is considered as a whole and a lot of inputs must be given a value in each test. Moreover, tests are generated independently on the basis that a test should be generated for each fault not yet covered by a previously found test. On the other hand, each circuit may contain many identical el- ements. Many faults are thus in fact alike but they affect a different part of the circuit. It is tempting to take advan- tage of this. If it is possible to generate a test for a circuit out of known tests for each part of the circuit, then it is only