1446 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 6, JUNE 2007 Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study Geert Eneman, Peter Verheyen, An De Keersgieter, Malgorzata Jurczak, and Kristin De Meyer, Senior Member, IEEE Abstract—This paper presents a study on the effectiveness of strained contact-etch-stop-layer (CESL) technologies in aggres- sively scaled dense structures. The focus is on nested transistors, which is a technologically very important structure that consists of a chain of gates on one active area. It will be shown that the two main channel stress components introduced by CESL, which are the vertical and parallel stresses, have a different sensitivity toward layout variations, which accordingly leads to different scaling guidelines to obtain a layout-insensitive strained CESL technology. Decreasing the CESL thickness is not enough for technology scaling; also, adapting the spacer dimensions is indis- pensable to scale a strained CESL technology from one technology node to the next. Index Terms—MOSFET, strained-silicon. I. INTRODUCTION T HE USE of mechanical strain has become a significant booster for silicon CMOS technology over the last five years. Strain changes the semiconductor’s band structure and modulates the conduction mass and intervalley and interband scattering properties of electrons and holes. This in turn can improve or degrade the characteristics for n- and p-type MOSFETs. One promising technique to introduce strain inside a transis- tor channel is the use of a silicon-nitride contact-etch-stop layer (CESL) with an intrinsic stress [1]–[8]. This layer is deposited in a CMOS flow after the source/drain (S/D) and gate silici- dation module, and serves as a stopping layer for the contact etching between the first level of metal and the transistor’s S/D and gate regions. CESL has a typical thickness of 20 nm and can contain up to 3 GPa of tensile or compressive stress, depending on the deposition conditions. The intrinsic stress inside the CESL translates into a stress state in the MOS channel. For short-channel transistors, a CESL with tensile intrinsic stress improves the nMOS performance, while a compressive intrinsic stress is beneficial for the pMOS behavior [1], [3], [7], [8]. Manuscript received November 27, 2006; revised February 22, 2007. The review of this paper was arranged by Editor V. R. Rao. G. Eneman is with the Interuniversity Microelectronics Center (IMEC), 3001 Leuven, Belgium. He is also with the ESAT-INSYS, Katholieke Universiteit Leuven, 3000 Leuven, Belgium, and with the Fund for Scientific Research, 1000 Brussels, Belgium. P. Verheyen, A. De Keersgieter, and M. Jurczak are with the Interuniversity Microelectronics Center (IMEC), 3001 Leuven, Belgium. K. De Meyer is with the Interuniversity Microelectronics Center (IMEC), 3001 Leuven, Belgium, and also with the ESAT-INSYS, Katholieke Univer- siteit Leuven, 3000 Leuven, Belgium. Digital Object Identifier 10.1109/TED.2007.896367 Fig. 1. Top-view layout of (left) a nested-transistor structure and (right) the corresponding electrical circuit. Similar to the SiGe S/D-technology, which is used to gener- ate a compressive channel stress in pMOS transistors, the CESL technology is a local stress technique. Both techniques have the advantage that the induced channel stress increases if the transistor length is scaled. On the other hand, the channel stress is a function of other structural dimensions as well. For CESL, important parameters are the CESL thickness, the transistor’s gate length and height, the intrinsic stress in the CESL, the spacer thickness [5], [9], and the active-area length and width [10]. These dependences complicate technology modeling and make a thorough understanding of CESL-induced stress indis- pensable for the design of digital and analog circuits. The purpose of this paper is to investigate the sensitivity of CESL-induced stress toward one specific important dimension: the active-area size and poly-to-poly length in aggressively scaled nested transistors. A nested-transistor structure is a chain of gates on one active area, which is separated by a distance of L p/p , which is the poly-to-poly length. This structure is a basic building block in CMOS technology (Fig. 1). It is intuitively clear that in scaled nested structures, the amount of CESL between the consecutive poly lines is reduced, which may lead to a decreased effectiveness of the technology. The stress simulations in this paper are performed with the finite-element simulator Taurus-Process of Synopsys [11]. The focus is on short-channel transistors (L g < 50 nm), and we use the stress in the center of the channel, 1 nm below the silicon surface (Fig. 2), as a measure for the CESL-induced stress. The goal is to indicate how channel stress changes as a function of active-area length and to point out the essential differences between the two stress components induced by CESL in the channel, the parallel and vertical stresses. All simulated nested 0018-9383/$25.00 © 2007 IEEE