IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 7, JULY 2011 2061 O FF -State Degradation of High-Voltage-Tolerant nLDMOS-SCR ESD Devices Alessio Griffoni, Member, IEEE, Shih-Hung Chen, Steven Thijs, Member, IEEE, Ben Kaczer, Jacopo Franco, Dimitri Linten, Member, IEEE, An De Keersgieter, and Guido Groeseneken, Fellow, IEEE Abstract—The OFF-state degradation of n-channel laterally diffused metal–oxide–semiconductor (MOS) silicon-controlled- rectifier electrostatic-discharge (ESD) devices for high-voltage applications in standard low-voltage complementary MOS tech- nology is studied. Based on experimental data and technology computer-aided design simulations, impact ionization induced by conduction-band electrons tunneling from an n + poly-Si gate to an n-well is identified to be the driving force of device degradation. Device optimization is proposed, which improves both OFF-state and ESD reliability. Index Terms—Charged device model (CDM), electrostatic dis- charge (ESD), human body model (HBM), input/output, laterally diffused metal–oxide–semiconductor (LDMOS), mixed signal, re- liability, silicon-controlled rectifier (SCR), transmission line puls- ing (TLP). I. I NTRODUCTION T HE integration of high-voltage (HV) and power compo- nents into standard logic complementary metal–oxide– semiconductor (CMOS) is one of the most important means of developing cost-effective system-on-a-chip solutions in the field of integrated CMOS–microelectromechanical sys- tems (MEMS), line drivers, universal serial bus interfaces, nonvolatile memory devices, display and light-emitting-diode drivers, 3-D stacked integrated circuits (ICs), automotive, etc. The HV-tolerant circuit design should be allowed to span the entire design space that the logic design enjoys. However, CMOS technology scaling imposes the reduction of power supply voltage to reduce power consumption and meet the reliability of ultrathin gate oxides (GOXs). As a consequence, Manuscript received December 2, 2010; revised March 16, 2011; ac- cepted March 16, 2011. Date of publication May 5, 2011; date of current version June 22, 2011. This work was supported in part by the follow- ing core and strategic partners of Interuniversity Microelectronics Center’s nanoelectronics R&D platform toward (sub-)22-nm complementary metal– oxide–semiconductor: Intel Corporation, Micron Technology Inc., Panasonic Corporation, Samsung Electronics, Taiwan Semiconductor Manufacturing Company, Elpida Memory Inc., Hynix Semiconductor, Sony Corporation, Fujitsu Limited, Powerchip Technology Corporation, and STMicroelectronics. The review of this paper was arranged by Editor M. Darwish. A. Griffoni, S. Thijs, B. Kaczer, D. Linten, and A. De Keersgieter are with the Interuniversity Microelectronics Center, 3001 Leuven, Belgium (e-mail: alessio.griffoni@imec.be; steven.thijs@imec.be; ben.kaczer@imec.be; dimitri. linten@imec.be; an.dekeersgieter@imec.be). S.-H. Chen, J. Franco, and G. Groeseneken are with the Interuniversity Mi- croelectronics Center, 3001 Leuven, Belgium, and also with the Departement Elektrotechniek, Katholieke Universiteit Leuven, 3001 Leuven, Belgium (e-mail: shih-hung.chen@imec.be; franco.jacopo@imec.be; guido. groeseneken@imec.be). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2011.2132760 reliability constraints such as electrostatic discharges (ESD), electrical overstress across a GOX, and hot-carrier degradation in input/output design can take away the flexibility to cover a broad range of operating voltages [1]–[5]. Several HV-tolerant implementations exist, such as cascoded devices, extended-voltage lateral bipolar junction transistors (BJTs), self-aligned laterally diffused MOS (LDMOS) and nonself-aligned devices with an extended drain [i.e., drain- extended MOS(DEMOS)], either by reusing existing CMOS layers or by adding extra implant layers [1], [2], [6]–[12]. LDMOS and DEMOS in particular are HV devices that can be easily integrated with a standard CMOS process in sub-100-nm node technology [13]. The ESD protection of these HV-tolerant devices is very critical [11], [12], [14]–[19]. Several techniques have been introduced to improve ESD robustness, e.g., high-resistance- body shallow trench isolation (STI) [20], substrate biasing [12], source ballasting [21], and embedding an additional diffusion region that forms a parasitic silicon-controlled rectifier (SCR) structure with reversible snapback capabilities [22]. This lat- ter device, which is also known as an n-channel LDMOS (nLDMOS)-SCR, is one of the most robust ESD protections since it has excellent clamping capabilities and ESD area performance. An in-depth ESD study of HV-tolerant nLDMOS- SCR devices in sub-100-nm CMOS technology was been car- ried out by the authors in [23]. HV-tolerant devices are often prone to reliability issues dif- ferent from those of core devices [24], [25]. The degradation of I/O devices is usually studied for ON-state conditions [26]– [29]. However, Varghese et al. and Shrivastava et al. have recently pointed out that nDEMOS devices exhibit the worst degradation during OFF-state operation compared with an ON- state one [29]–[32]. Therefore, it is crucial to investigate OFF- state degradation also in our nLDMOS-SCR devices. In this paper, we will present an experimental study coupled with technology computer-aided design (TCAD) simulations [33] on the OFF-state degradation of nLDMOS and nLDMOS- SCR devices, extending the physical insight and the optimiza- tion of the work of Varghese et al. and Shrivastava et al. [29]–[32], [34]. We will also optimize both OFF-state reliability and ESD performance by changing the gate-to-n-well overlap length. II. DEVICES AND EXPERIMENTS nLDMOS-SCR devices (see Fig. 1) were manufactured in standard 90-nm CMOS technology. The devices have a SiO 2 0018-9383/$26.00 © 2011 IEEE