System-level metrics for hardware/software architectural mapping Fabrizio Ferrandi, Pierluca Lanzi, Donatella Sciuto, Mara Tanelli Dip. di Elettronica e Informazione, Politecnico di Milano P.zza L. da Vinci 32, 20133 Milano,ITALY E-mail: ferrandi,lanzi,sciuto,tanelli @elet.polimi.it Abstract The current trend in Embedded Systems (ES) design is moving towards the integration of increasingly complex ap- plications on a single chip, while having to meet strict mar- ket demands which force to face always shortening design times. In general, the ideal design methodology shall sup- port the exploration of the highest possible number of al- ternatives (in terms of HW-SW architectures) starting in the early design stages as this will prevent costly correction ef- forts in the deployment phase. The present paper will pro- pose a new methodology for tackling the design exploration problem, with the aim of providing a solution in terms of op- timal partitioning with respect of the overall system perfor- mance. 1. Introduction Embedded Systems (ES) design has undergone several deep transformations during the past few years. The most relevant concern is raising of the abstraction level of the system modeling, made possible by recent evolutions in the description languages, as it makes it possible to achieve faster time to market, by smoothing the design process and enabling component reuse. Another trend in the evolution of the design formalisms is the use, as basis for the sys- tem design specification, of typical software languages such as C and C++. The introduction of new description lan- guages for the embedded systems applications such as Sys- temC, poses new problems, mainly due to their ability to express system models at levels of abstractions not possi- ble before. The choice of an architecture, i.e. of a collec- tion of components that can be either SW programmable, re-configurable or customized, is one of the important steps in design. The proposed methodology relies on the separa- tion between [12]: function (what the system is supposed to do) and architecture (how it does it) and between com- munication and computation. Our work aims at defining a high-level methodology for finding an optimal partitioning, trying to overcome some limitations inherent in present ap- proaches; in particular, our approach will focus on perform- ing all the estimation phases at the highest possible level of abstraction, before committing to a specific implemen- tation. All the estimations will be the result of a dynamic analysis of the system, performed via simulation, that con- siders both local and global features of the system under study. A formal model will be introduced for describing the system and for encompassing the proposed communication model, which will provide a theoretical mean for describing the different data exchange mechanisms commonly used in a mixed hardware-software architecture. The optimal parti- tioning will be found by means of a combination of mul- tivariate statistical techniques and Learning Classifier Sys- tems, The methodology is composed of three steps: software performance estimation, hardware and communication per- formance estimation and the final partitioning; each of them will be described in the next sections, highlighting their mo- tivations and relations. 2. Related Works In the following we will present a survey of the most im- portant approaches to the problem of finding a suitable par- titioning for deciding which parts of a system have to be implemented in hardware and which in software. We can identify four different elements that distinguish an approach from another: the ”formal model” chosen to describe the system specification, the ”granularity” at which the speci- fication itself is analyzed, the ”cost function” on the basis of which the design choices are performed and the ”algo- rithm” chosen for the identification of the optimal partition- ing according to the above metrics. The first significant work dates back to 1993 [3], and it represents one of the first approaches tackling the com- plete design of embedded applications. The system is de- scribed at the behavioral level by means of an appropriate specification language, whose underlying formal model is a CDFG and the chosen granularity is the operation. The operation delays (needed for performance estimation) are provided separately for hardware and software implemen- tations, based on the type of hardware to be used and on the processor used to run the software. The partitioning algo- rithm focuses the attention on minimizing communication Proceedings of the Second IEEE International Workshop on Electronic Design, Test and Applications (DELTA’04) 0-7695-2081-2/04 $ 20.00 © 2004 IEEE