INVITED PAPER Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs In 3D integrated circuits, analog, digital, flash and DRAM wafers are processed separately, then brought together in an integrated vertical stack. By Robert S. Patti, Member IEEE ABSTRACT | Three-dimensional integrated circuits (3-D ICs) offer significant improvements over two-dimensional circuits, and promise a solution to the severe problems that are being, and will be, encountered as monolithic process geometries are reduced to below 65 nm. Several methods associated with the fabrication of 3-D ICs are discussed in this paper, and the techniques developed by Tezzaron Semiconductor Corp., are described in detail. Four successful 3-D ICs are described, along with the anticipated benefits of applying 3-D design to future system-on-chip (SoC) devices. KEYWORDS | Integrated circuit interconnections; three- dimensional integrated circuits (3-D ICs) I. INTRODUCTION The evolution of the integrated circuit (IC) has begun to slow. In the past, technical difficulties presented real but surmountable barriers; now, perhaps, we are approaching a domain where physics forbids smaller gate technologies. Fig. 1 shows the rapid increase in delay time caused by the interconnect as geometries shrink. Somewhere between the 130- and 110-nm process nodes, the increased delay of the wires outweighs the increased performance of smaller transistors. Low-K di- electric wiring allows 90-nm performance to improve slightly over 130 nm, but ultralow K will, at best, hold the line for 65-nm designs. Beyond 65 nm, the picture is grim. Even if we can solve the problems of ever-shrinking geometries, will the result justify the cost? Cost issues surrounding reduction of the dielectric constant using ultralow-K materials are a case in point. Rick Hill, CEO of Novellus, described process geometries smaller than 65 nm as Btechnologically feasible, but not economically feasible[ [2]. Three-dimensional ICs (3-D ICs) offer a promising solution, reducing both footprint and interconnect length without shrinking the transistors at all. Dr. Susan Vitkavage, 3-D IC Project Manager for SEMATECH, commented that B3-D wiring could be a viable replace- ment for 2-D wiring when the continued push to reduce RC makes 2-D wiring cost prohibitive, and 3-D IC shows a cost benefit[ [3]. Three-dimensional ICs are perhaps the best hope for carrying ICs further along the path of Moore’s Law. In addition to obvious size benefits and possible cost bene- fits, they can address issues of heterogeneous integration, power and performance, and logical span of control. A. Heterogeneous Integration Integrating an entire system onto a single piece of siliconVa system-on-chip (SoC)Voften requires integrat- ing analog with digital, flash, and DRAM. The goal of such Manuscript received October 27, 2005; revised January 6, 2006. The author is with Tezzaron Semiconductor, Naperville, IL 60563 USA (e-mail: rpatti@tezzaron.com). Digital Object Identifier: 10.1109/JPROC.2006.873612 Fig. 1. Gate and interconnect delays as a function of gate technology [1]. 1214 Proceedings of the IEEE | Vol. 94, No. 6, June 2006 0018-9219/$20.00 Ó2006 IEEE