Parametric Circuit Representation Using Inductive Boolean Functions* Aartl Gupta and Allan L. Fisher School of ComputerScience CarnegieMellon University Pittsburgh,PA 15213-3891. Abstract. We have developed a methodologybased on symbolicmanipulation of indue- five Boolean functions(IBFs) for formal verification of inductively-defined hardware. This methodologycombines the techniquesof reasoning by induction and symbolic tautology- checking in an automated and potentiallyefficientway. In this paper, we describe a com- ponentof this methodologythat regards varioesmechanisms used to represent inductively- definedcircuitsin the form of IBFs. The focusis on general parameterization issues, such as multiple parameterfunctions,multipleoutput functions, interaction of different parameters for supporting compositionsetc. These mechanisms,which may be useful in other appli- cations involving parametric circuit descriptions,are KlusU'atedthrough practical circuit examples along with preliminary results. We also describe an application of our formal verificationmethodology,where a proof by inductionis performed by automatic symbolic manipulation of parametriccircuit representations. 1 Introduction The high level of complexity of current hardware systems has led to an interest in formal methods for proving their correctness. We have developed a methodology based on symbolic manipulation of inductive Boolean functions (IBFs) for formal verification of inductively-definedhardware, i.e. circuits where the structure can be described inductively (iterativeiy, or recursiveiy) in terms of size parameters. Since reuse of existing designs has become an important issue in practice, use of parametric designs in the form of standard libraries has been emphasized as an emerging trend [12]. By directly addressing the issue of parameterization in our approach, as described in this paper, we provide the necessary framework for representation and verification of such designs. To provide a perspective for the research described in this paper, we start with a brief background description of our verification methodology. 1.1 Motivation Previous verification work with parametric descriptions of circuits includes reasoning by in- duction both in theorem-proving systems [7, 13, 16, 20], and within model checking/language- containment paradigms [9, 17, 21] (an extended bibliography can be found in a recent sur- vey [14]). The main advantage with these approaches is that a single proof serves to establish the functional or behavioral correctness of an entire family of circuits. However, most available approaches are semi-automated, typically requiring user guidance and heuristic search for a proof. * This research was sponsored by the Avionics Laboratory, Wright Research and Development Center, AeronauticalSystemsDivision(AFSC), U.S. Air Force, Wright-Patterson AFB, Ohio 45433-6543under Contract F33615-90-C-1465, ARPA Order No. 7597. The views and conclusions contained in this document are those of the author and should not be interpreted as representingthe officialpolicies,either expressed or implied,of the U.S. government.