JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.1, FEBRUARY, 2015 http://dx.doi.org/10.5573/JSTS.2015.15.1.041 Manuscript received Aug. 25, 2014; accepted Nov. 13, 2014 A part of this work was presented in Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Kanazawa in Japan, July 2014 1 Dep. Electronics Engineering, Chungnam National Univ., Daejeon, Korea. 2 Dep. School of Integrated Technology, Yonsei Univ., Incheon, Korea *E-mail : hdlee@cnu.ac.kr, Tel : +82-42-821-6868 A Study of the Dependence of Effective Schottky Barrier Height in Ni Silicide/n-Si on the Thickness of the Antimony Interlayer for High Performance n-channel MOSFETs Horyeong Lee 1 , Meng Li 1 , Jungwoo Oh 2 , and Hi-Deok Lee 1,* Abstract—In this paper, the effective electron Schottky barrier height (Ф Bn ) of the Ni silicide/n- silicon (100) interface was studied in accordance with different thicknesses of the antimony (Sb) interlayer for high performance n-channel MOSFETs. The Sb interlayers, varying its thickness from 2 nm to 10 nm, were deposited by radio frequency (RF) sputtering on lightly doped n-type Si (100), followed by the in situ deposition of Ni/TiN (15/10 nm). It is found that the sample with a thicker Sb interlayer shows stronger ohmic characteristics than the control sample without the Sb interlayer. These results show that the effective Ф Bn is considerably lowered by the influence of the Sb interlayer. However, the current level difference between Schottky diodes fabricated with Sb/Ni/TiN (8/15/10 nm) and Sb/Ni/TiN (10/15/10 nm) structures is almost same. Therefore, considering the process time and cost, it can be said that the optimal thickness of the Sb interlayer is 8 nm. The effective Ф Bn of 0.076 eV was achieved for the Schottky diode with Sb/Ni/TiN (8/15/10 nm) structure. Therefore, this technology is suitable for high performance n-channel MOSFETs. Index Terms—Nckel silicide, antimony interlayer, Schottky diode, effective Schottky barrier height, n- channel MOSFETs I. INTRODUCTION Over the last several decades, metal oxide semiconductor field effect transistors (MOSFETs) have been continuously scaled down to improve device performance and to reduce the device cost per unit wafer area. As the channel length of MOSFETs has been scaled down to sub-0.1 μm, the ultra-shallow source/drain (S/D) junction depth has been required to suppress short channel effects (SCEs) [1-3]. However, ultra-shallow S/D junction increases the sheet resistance (R sh ), which can degrade device performance [4]. To solve this problem, silicides have been used to reduce R sh in the S/D regions [5, 6]. Nickel silicide (NiSi) is one of the candidates, which has recently gained great attention. NiSi has a low resistivity (14-16 μΩ-cm) and consumes less silicon than other silicides like titanium silicide (TiSi 2 ) and cobalt silicide (CoSi 2 ) [7, 8]. Therefore, it is suitable in ultra-shallow S/D junctions. However, the relative contribution of contact resistance (R c ) to S/D series resistance (R series ) has significantly increased as devices have undergone extreme scaling [3, 9]. Thus, decreasing R c has become one of the issues for high performance MOSFETs. R c at the silicide/silicon (Si) interface has been reported to be closely related to the effective Schottky barrier height (Ф B ) [3]. For this reason, it is also important to reduce the effective Ф B at the silicide/Si interface in S/D regions. In this paper, we describe a method to reduce the