2578 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 47, NO. 6, NOVEMBER/DECEMBER 2011 Monitoring Solder Fatigue in a Power Module Using Case-Above-Ambient Temperature Rise Dawei Xiang, Li Ran, Senior Member, IEEE, Peter Tavner, Senior Member, IEEE, Angus Bryant, Member, IEEE, Shaoyong Yang, Member, IEEE, and Philip Mawby, Senior Member, IEEE Abstract—Condition monitoring is needed in power elec- tronic systems as a cost-effective means of improving reliability. Packaging-related solder fatigue has been identified as one of the main root causes of power electronic module failures. This paper presents a method to monitor solder fatigue inside a module by identifying the increase of internal thermal resistance due to that solder fatigue, taking account of the masking effect of the variable operating point. It is assumed that the total loss in the module increases as junction temperature rises, causing an increase in case-above-ambient temperature rise, which can be measured. A dynamic thermal model of the heat sink is utilized to estimate the power loss from temperature measurements, while a device power loss model is developed to estimate the internal thermal resistance by considering the converter electrical loading. Experiment and simulation are used to demonstrate the concept and verify the method. Index Terms—Condition monitoring, losses, power semiconduc- tor devices, reliability, solder fatigue, thermal network. I. I NTRODUCTION P OWER ELECTRONIC converters are key components in many safety-critical high-reliability systems operating in harsh and uncertain conditions. Designers try to improve reliability using thermal management or derating of devices [1]–[3]. Such means may not be attractive in today’s environ- ment where space, efficiency, and cost are all under pressure. Regardless of the design, failures can still happen. Condition monitoring provides an alternative approach which has proven effective for other electrical components [4], [5]. While, for Manuscript received October 31, 2010; revised April 3, 2011; accepted June 14, 2011. Date of publication September 19, 2011; date of current version November 18, 2011. Paper 2010-PEDCC-476.R1, presented at the 2010 IEEE Energy Conversion Congress and Exposition, Atlanta, GA, September 12–16, and approved for publication in the IEEE TRANSACTIONS ON I NDUSTRY APPLICATIONS by the Power Electronic Devices and Components Committee of the IEEE Industry Applications Society. This work was supported by the U.K. Engineering and Physical Sciences Research Council under Grants EP/E02744X/1 and EP/E026923/1: COMPERE. D. Xiang was with the School of Engineering and Computing Sciences, Durham University, Durham DH1 3LE, U.K. He is now with Chongqing University, Chongqing 400044, China (e-mail: xdw_cqu@sina.com). L. Ran and P. Tavner are with the School of Engineering and Com- puting Sciences, Durham University, Durham DH1 3LE, U.K. (e-mail: li.ran@durham.ac.uk; peter.tavner@ durham. ac.uk). A. Bryant and S. Yang were with the School of Engineering, University of Warwick, Coventry CV4 7AL, U.K. They are now with Converteam U.K. Ltd., Warwickshire, CV21 1BU, U.K. (e-mail: atb230@googlemail.com; sxy188@googlemail.com). P. Mawby is with the School of Engineering, University of Warwick, Coventry CV4 7AL, U.K. (e-mail: p.a.mawby@warwick.ac.uk). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIA.2011.2168556 power electronics, condition monitoring is only at an embryonic stage, there is increasing interest in industry [3], [6]–[9]. Packaging-related solder fatigue is a main root cause of intelligent power module (IPM) failures [3], [9], [10] and can happen in the solder layer between the chip and substrate or between the substrate and baseplate. This is due to temperature cycling and mismatch of the coefficients of thermal expansion, which induces shear stresses in the solder layers, leading to cracks or voids [11]. Solder fatigue reduces the effective area for heat to be conducted out of the IPM [12]. A 20% in- crease of the internal thermal resistance from the junction to case (R thP_jc ) is often adopted as the threshold value [13]. “Solder-free” module designs, using spring-pressure contacts and diffusion sintering, are being developed [14]. The failure rates should be lower, although new failure mechanisms may be introduced. However, since most IPMs today cannot be solder free, condition monitoring of such IPMs is needed, and with this aim in mind, this study pursues a technique to monitor the solder condition inside an IPM. Reference [6] describes a unit in an IPM for detecting the change of the internal thermal resistance. It measures internal temperatures and correlates this to the power loss estimated from the device current measurement with switching losses ignored. The ON-state and switching losses can be obtained from a model [15], [30] but the result depends on device characteristics. While the substrate temperature can be sensed in some IPMs with an integrated sensor [16], the junction tem- perature, which is needed for calculating the thermal resistance, is difficult to access [7], [17]–[21]. A sensor can be placed close to the junction, but this is intrusive and the response is affected by the sensor location [17], [18]. The method has not been used outside laboratories. Model-based estimation deduces the junction temperature from case temperature, device losses, and thermal resistance [19]. Apart from the difficulty of loss esti- mation, the method is not ideal for solder fatigue monitoring as the fatigue is not represented in the thermal model. Indeed, the thermal resistance increases as the solder area decreases with age. Alternatively, the junction temperature could be deduced from temperature sensitive device parameters [7], [18], [20], [21]. Such a method is as yet immature, particularly in the following aspects. 1) IPM modification is needed. Additional circuitry is used in [7] and [18] to measure the ON-state voltage. This can be problematic with the dramatic change of the mea- surand before and after switching. The top-leg insulated gate bipolar transistors (IGBTs) present a challenge for 0093-9994/$26.00 © 2011 IEEE