Substrate Noise Influence on Circuit Performance in Variable Threshold-Voltage Scheme Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori*, Kenji Matsuo*, Masakazu Kakumu*, and Takayasu Sakurai System ULSI Engineering Laboratory, Toshiba Corp., Kawasaki, Japan * Semiconductor Group, Toshiba Corp., Kawasaki, Japan Abstract - This paper investigates substrate noise influence on circuit performance in a variable threshold- voltage scheme (VT scheme) where threshold voltage is dynamically varied by substrate-bias control to reduce active power dissipation. It is experimentally examined that substrate-bias can be controlled stably with very few substrate-contacts. Measured tracking jitter of a delay- locked loop implemented by interconnections in an 8mm- square gate array does not degrade even when substrate- contacts are removed except for one at every strip of p-sub and n-well. A 2mm-square discrete cosine transform core processor with no substrate-contact except in its periphery operates at supply voltages from 1.3V to above 3V even though it employs small-swing differential dynamic pass-transistor logic. No performance degradation nor latchup is observed in these chips even when 100kΩ resistance is added to the substrate. These experimental results demonstrate noise immunity of the VT scheme, and indicate the possibility that the VT scheme can be applied to existing macro design easily. I. INTRODUCTION Lowering both of the supply voltage, V DD , and threshold voltage, V th , enables high-speed, low-power operation. This approach, however, raises three problems; 1) degradation of worst case speed due to V th fluctuation in low V DD , 2) increase in standby power dissipation in low V th , and 3) disablement to sort out defective chips by monitoring the quiescent power supply current (I DDQ ). Two circuit schemes to solve these problems were proposed. One is to employ two V th ; low V th for fast circuit operation and high V th for cutting internal power supply voltage in a standby mode [1]. This scheme, however, solves only the standby power problem, and Fig. 1 Variable Threshold-Voltage (VT) scheme. requires very large transistors for the power supply control to impose area and yield penalties, otherwise circuit speed degrades. Furthermore it cannot be applied to memory elements. The other scheme is to dynamically vary V th through substrate-bias, V BB ; hence the name variable threshold-voltage scheme (VT scheme). As illustrated in Figure 1, V BB is controlled so as to compensate V th fluctuations in an active mode, while in a standby mode and in the I DDQ testing deep V BB is applied to increase V th and cut off leakage. Several circuit implementations were developed [2-4]. The VT scheme can solve the three problems all together, requires no large transistor, and can be applied to both logic gates and memory elements. However, it may impose an area penalty for routing the substrate-contacts globally, compared to the conventional layout design where they are connected to power lines locally. Addition of the substrate-contact interconnections makes application of the VT scheme to existing macro design impractical. Without clear understanding of substrate noise influence on circuit performance we cannot figure out how many substrate- contacts we should place and route. ISLPED 1996 Monterey CA USA 0-7803-3571-8/96/$5.00  1996