1 Scientific RepoRts | 7:45556 | DOI: 10.1038/srep45556 www.nature.com/scientificreports scaling trends and performance evaluation of 2-dimensional polarity-controllable FETs Giovanni V. Resta 1 , Tarun Agarwal 2,3 , Dennis Lin 2 , Iuliana p. Radu 2 , Francky Catthoor 2,3 , Pierre-Emmanuel Gaillardon 4 & Giovanni De Micheli 1 Two-dimensional semiconducting materials of the transition-metal-dichalcogenide family, such as Mos 2 and Wse 2 , have been intensively investigated in the past few years, and are considered as viable candidates for next-generation electronic devices. In this paper, for the frst time, we study scaling trends and evaluate the performances of polarity-controllable devices realized with undoped mono- and bi-layer 2D materials. Using ballistic self-consistent quantum simulations, it is shown that, with the suitable channel material, such polarity-controllable technology can scale down to 5 nm gate lengths, while showing performances comparable to the ones of unipolar, physically-doped 2D electronic devices. Miniaturization of silicon-based CMOS devices has been the main drive of the silicon industry for nearly half a century, and has allowed an exponential increase in computing power, as embodied by Moore’s law. With phys- ical gate lengths slowly approaching 10 nm, the limits of current silicon technology are becoming increasingly difcult to overcome, and new semiconductor materials and novel device concepts have been studied, that could ultimately outperform silicon 1,2 . Among the materials that have been studied as a semiconducting channel for charge-based devices, 2-dimensional (2D) materials of the transition-metal-dichalcogenide (TMDCs) family 3 are one of the most exciting and promising opportunities, thanks to their electrical and physical properties 4,5 . Te presence of a sizeable bandgap (1~2 eV) makes TMDCs materials appealing for electronics applications, as it allows us to realize devices with low leakage foor and high ON/OFF current ratios 6–10 . Amongst the other remarkable features of TMDCs, their layered structure provides 2D flms of controllable uniform thickness with dangling-bonds free interfaces. Moreover, their extreme thinness and low in-plane dielectric constant alleviate short-channel efects (SCE) and drain-induced-barrier-lowering (DIBL) 11,12 , which are detrimental to device per- formances. Te high efective mass of charge carriers (especially with respect to III-V materials) helps reducing direct source-to-drain tunneling at ultra-scaled dimensions 13,14 , providing a better control of the device OFF-state by the gate terminals. Furthermore, 2-dimensional materials are attractive for monolithic integration on top of CMOS or multi-stacking of TMDCs layers 15 , thanks to the low thermal budget needed in the fabrication process. Te most studied material of the TMDCs family, MoS 2 , has proven to be a viable solution for the realization of n-MOS transistors 6,7 , and ultra-scaled n-type devices have been recently demonstrated 16,17 . Short channel MoS 2 p-type FETs fabricated with doped silicon contacts 18 have also been reported, however, MoS 2 has not experi- mentally shown any ambipolar behaviour, which is essential for the realization of polarity-controllable devices. Reports of ambipolar contacts to MoS 2 are in fact limited to devices realized on thick fakes on a PMMA sub- strate 19 or devices gated with ionic liquids 20 . So far, the most promising material for the realization of both n- and p-type devices is arguably tungsten diselenide (WSe 2 ), for which high carrier mobility 21 , ambipolar behavior 22 and CMOS devices have been reported experimentally 8,9 . Te ambipolar behavior of WSe 2 has recently been exploited to realize polarity-controllable devices, based on undoped Schottky-barrier (SB) double-independent-gate (DIG) FETs 23 , as shown in Fig. 1. Te device, presented in Fig. 1a, was experimentally realized on a WSe 2 fake, and bur- ied DIG gates were used to control its polarity and ON/OFF status 23 . Te need for physical doping of the devices 1 integrated System Laboratory (LSi), School of engineering, École Polytechnique fédérale de Lausanne (ePfL), cH- 1015 Lausanne, Switzerland. 2 IMEC, Kapeldreef 75, B-3001 Leuven, Belgium. 3 KU Leuven, Celestijnenlaan 200D, B-3001, Leuven, Belgium. 4 Laboratory of NanoIntegrated Systems (LNIS), Department of Electrical and Computer Engineering, University of Utah, Salt-Lake City, Utah 84112, USA. Correspondence and requests for materials should be addressed to G.V.R. (email: giovanni.resta@epf.ch) or I.P.R. (email: iuliana.radu@imec.be) or P.-E.G. (email: pierre-emmanuel.gaillardon@utah.edu) Received: 24 November 2016 Accepted: 27 February 2017 Published: 30 March 2017 OPEN