Current-Mode Analog Integrated Circuit for Focal-Plane Image Compression Fernanda D. V. R. Oliveira, Hugo L. Haas, Jos´ e Gabriel R. C. Gomes and Antonio Petraglia Universidade Federal do Rio de Janeiro – COPPE / Electrical Engineering Program Rio de Janeiro, RJ 21941-972, Brazil Email: (fernanda, hugohaas, gabriel, antonio@pads.ufrj.br) Abstract—The interest in focal-plane processing techniques, by which image processing is carried out at pixel level, has increased since the advent of active pixel sensors in the middle 90’s. By sharing processing circuitry by a group of neighboring pixels such techniques enable high-speed imaging operation and massive parallel computation. Focal-plane image compression is particularly interesting, because it allows for further reduc- tion in data rates. The proposed approach also benefits from processing currents rather than voltages, which not only suits current-mode APS imagers, but also enables the circuits to operate at low voltage supply levels and achieve high speed. Moreover, arithmetic computations such as additions and scaling are easily implemented in current mode. Whereas current-mode imaging architectures produce higher fixed pattern noise (FPN) figures than their voltage-mode counterparts, low FPN can be achieved by applying correlated double sampling (CDS) and gain correction techniques. This work presents a 32 × 32 imaging integrated circuit that captures and compresses gray scale images on the focal plane of the image sensors using analog circuits that implement, for every 4 × 4 pixel block, differential pulse-code modulation, linear transform, and vector quantization. Other processing functions implemented in the chip are CDS, analog convolutions and A/D conversion. Theoretical details and circuit designs are described, as well as the test setup of the chip fabricated in a 0.35 μm CMOS process. Experimental results and photographs captured by the chip are shown to validate the technique. The CMOS imager compresses captured images at 0.94 bits/pixel for an overall power consumption below 40 mW (white image), which is equivalent to approximately 36 μW per pixel. Using photographs taken from bar-target pattern inputs, it is shown that details up to 2 cycles/cm are preserved in the decoded images. Index terms – CMOS image sensor, imager, focal plane, image processing, compression, DPCM, VQ I. I NTRODUCTION The main feature of CMOS image sensors is that they allow the introduction of processing hardware at the pixel level. Using this characteristic, it is possible to extract from the image only the desired data, thereby reducing the output data rate. The analog processing has also the advantage of allowing high speed operation. Owing to these features, in the last few years there has been a strong interest in CMOS image sensors, called here as imagers [1]-[8]. The imager described in this paper is capable of com- pressing a gray scale image using analog hardware [9]. The This work was supported by Brazilian higher education and research funding agencies: CAPES, CNPq, and FAPERJ. o(n) s 1 (n) s 2 (n) s 3 (n) s 4 (n) x 1 (n) x 2 (n) x 3 (n) x 4 (n) |e(n)| e(n) s(n) p 1 (n) p 2 (n) p 3 (n) p 4 (n) SQ VQ 16-pixel matrix b 01 (n) b 02 (n) b 03 (n) b 1 (n) b 2 (n) b 3 (n) b 4 (n) b 5 (n) b 6 (n) b 7 (n) ˆ s(n + 1) ˆ s(n) b 00 (n) -1 Reconstruction DPCM Absolute Value Fig. 1. Image compression algorithm block diagram, for a 4 × 4 pixel block. compression is lossy and the method used, which is based on DPCM and VQ, is briefly reviewed in Section II. To decode the bits produced by the chip, we use the decoder described in Section III. The pseudo-code necessary to generate the image is also shown in this section. Previous experimental results from the chip can be found in [10]. The main purpose of this paper is to report theoretical and experimental results that show the contributions of the DPCM and VQ analog circuits in producing the the pictures taken by the chip. The pseudo-code in Section III describes the theoretical contributions and shows how the DPCM and VQ results are put together to create the final image. Section IV presents the circuit that implements the DPCM algorithm. Experimental results are presented in Section V. Concluding remarks are made in Section VI. II. I MAGE COMPRESSION ALGORITHM A description of the image compression algorithm is shown next. Additional details can be found in [9], [10]. To illustrate this description, Figure 1 shows an overall block diagram describing the interconnection of the three stages composing the image compression algorithm. 1) Initial setup: the image is divided into 4 × 4 pixel blocks. The 16 scalar values from the block are arranged into a 16 × 1 vector denoted as y(n). Compute the sum of all the values from y(n), thus generating the sum value s(n). The index n varies from 1 to 64 and represents the pixel-block index.