Effective work function control of metal inserted poly-Si electrodes on HfSiO dielectrics by in-situ oxygen treatment of metal surface Naomu Kitano a, b, * , Keisuke Chikaraishi a , Hiroaki Arimura a , Takuji Hosoi a , Takayoshi Shimura a , Takashi Nakagawa b , Heiji Watanabe a a Department of Material and Life Science, Graduate School of Engineering, Osaka University, 2-1 Yamada-oka, Suita, Osaka 565-0871, Japan b Canon ANELVA Corporation, 2-5-1 Kurigi, Asao-ku, Kawasaki, Kanagawa 215-8550, Japan article info Article history: Received 2 February 2012 Received in revised form 14 May 2012 Accepted 19 May 2012 Available online 30 May 2012 Keywords: High-k dielectrics Metal electrode In-situ process Effective work function Oxygen vacancy Si diffusion abstract We fabricated novel poly-Si/TiN/HfSiO/SiO 2 gate stacks by using an in-situ oxygen treatment process of a TiN electrode surface in order to suppress Si diffusion from poly-Si upper layer during post deposition annealing (PDA). The Si depth profile after PDA showed that no Si diffused into oxidized stacks due to the formation of TiON layers as a Si diffusion barrier. Furthermore, a high effective work function (EWF) of 4.94 eV was obtained from the oxidized stack even after PDA at 1000  C. This high EWF is due not only to Si diffusion barrier formation but also to oxygen vacancy compensation by diffused-oxygen from the TiON layer. However, we observed significant growth of interfacial SiO 2 after high temperature annealing. These results indicate a trade-off relationship between EWF control and equivalent oxide thickness (EOT) scaling, and imply that an additional method for EWF modulation is required for scaled high-k devices. Ó 2012 Elsevier B.V. All rights reserved. 1. Introduction As metal-oxide-semiconductor field-effect transistors (MOS- FETs) are scaling down, the physical thickness of SiO 2 and SiON gate dielectrics has dropped below 1.5 nm. The gate leakage current due to direct tunneling though the ultrathin oxides has increased significantly. Therefore, high-permittivity gate dielectrics (high-k gate dielectrics) are indispensable for gate dielectrics. In addition, metal gate electrodes are required to eliminate the gate depletion that inherent in conventional polycrystalline silicon (poly-Si) gates. The combination of metal gate electrode with high-k dielectrics is thus a promising candidate technology for further improvement of MOSFETs. When metal/high-k gate stacks integrated with a gate- first process, change in effective work function (EWF) after activa- tion anneal is a serious concern, for p-FETs in particular [1]. This phenomenon, known as Fermi level pinning (FLP), is attributed to the formation of oxygen vacancy (V o ) in Hf-based dielectrics [2,3]. Moreover, when reduction materials, such as carbon, are in the gate stacks, it turns out that formation of V o is enhanced [4,5]. Suppression of V o formation in high-k dielectrics is the most important way to obtain the desired EWF. Previously, we proposed a physical vapor deposition (PVD)- based in-situ method for fabricating high-quality metal/high-k gate stacks [6]. We formed Hf-silicate (HfSiO) dielectrics by utilizing the solid phase interface reaction (SPIR) between ultrathin PVD-grown metal-Hf layers (typically 0.5 nm thick) and SiO 2 underlayers ranging in thickness from 1.3 to 1.8 nm [7]. Metal diffusion to the oxide underlayer induced by SPIR annealing forms high-quality HfSiO dielectrics, and the resultant equivalent oxide thickness (EOT) is smaller than that of the initial oxide thickness of SiO 2 underlayer. To precisely control the formation of interface silicate and reduce the impurities in the gate stacks, in-situ SPIR annealing was done without exposure to air using a cluster tool that consists of low-damage PVD equipment and an annealing module [6]. After the gate dielectrics formation, the wafers were transferred back to the PVD chamber to continuously deposit thick TiN electrodes by reactive sputtering using a Ti target and a N 2 /Ar gas mixture. By using this process, we reduced the carbon impurities in the gate stacks, and reduced the threshold voltage (V th ) and obtained excellent electrical properties for gate-first p-MOSFETs [8,9]. Recently, for the gate-first process, the thickness of metal gate reduced under 10 nm and thick poly-Si electrode is formed on the metal gate in general, which is known as metal inserted poly-Si * Corresponding author. Canon ANELVA Corporation, 2-5-1 Kurigi, Asao-ku, Kawasaki, Kanagawa 215-8550, Japan. Tel.: þ81 44 980 5136; fax: þ81 44 986 4237. E-mail address: kitano.naomu@canon-anelva.co.jp (N. Kitano). Contents lists available at SciVerse ScienceDirect Current Applied Physics journal homepage: www.elsevier.com/locate/cap 1567-1739/$ e see front matter Ó 2012 Elsevier B.V. All rights reserved. doi:10.1016/j.cap.2012.05.032 Current Applied Physics 12 (2012) S83eS86