A new CMP-less integration approach for highly scaled totally silicided (TOSI) gate bulk transistors based on the use of selective S/D Si epitaxy and ultra-low gates Markus Mu ¨ ller a, * , Alexandre Mondot b , Delphine Aime ´ b , Benoı ˆt Froment b , Alexandre Talbot b , Julien-Marc Roux b , Guillaume Ribes b , Yves Morand b , Sophie Descombes b , Pascal Gouraud b , Franc ¸ois Leverd b , Simone Pokrant a , Alain Toffoli c , Thomas Skotnicki b a Philips Semiconductors, 850, Rue Jean Monnet, 38926 Crolles Cedex, France b STMicroelectronics, 850, Rue Jean Monnet, 38926 Crolles Cedex, France c CEA-LETI, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France Received 22 November 2005; received in revised form 8 March 2006; accepted 15 March 2006 The review of this paper was arranged by G. Ghibaudo and T. Skotnicki Abstract In this paper, we present an innovative way of fabricating MOS transistors with totally Ni-silicided (Ni-TOSI) gates without any CMP step before the full gate silicidation process. The combination of the use of a hard-mask-capped ultra-low initial Si gate with a selective S/ D epitaxy step enables us to perform the total gate and junction silicidation in one single step similarly to a standard MOS flow. Full gate silicidation and well-controlled junction silicidation is achieved down to minimum gate lengths of 40 nm. Moreover, we show that the TOSI PMOS device performances are compatible with the 45 nm-node LP requirements. Reliability data is added demonstrating that no additional breakdown mechanisms occur after the TOSI process. Ó 2006 Elsevier Ltd. All rights reserved. Keywords: MOS transistor; Total gate silicidation; Ni silicide; Selective epitaxy; Metal gate 1. Introduction One of the greatest challenges of the scaling of CMOS transistors for future nodes is the appropriate scaling of the gate stack. As the scaling of the gate oxide is limited by the increase of the gate leakage, metallic gate solutions are desirable as they increase the gate capacitance simply by the suppression of the poly-depletion relaxing thus the scaling requirements on the gate oxide. Among the different approaches for metallic gate inte- gration, the TOSI (TOtally SIlicided) gate approach is widely investigated as a good alternative to the (dual) metal approach. In the ‘true’ metal gate approach, metal is deposited on the gate oxide, capped by poly-silicon and finally patterned to form the future gate electrodes, which is technologically challenging, especially if two different metals are to be integrated for the p- and n-type electrode. This difficulty is overcome by the TOSI process, where a first gate electrode is formed out of poly-Si in complete analogy to a standard transistor flow and transformed only later into metal by a complete silicidation process [1–3]. Moreover, in principle only one silicide material is needed 0038-1101/$ - see front matter Ó 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2006.03.033 * Corresponding author. Tel.: +33 4 76 92 33 18. E-mail address: markus.muller@philips.com (M. Mu ¨ ller). www.elsevier.com/locate/sse Solid-State Electronics 50 (2006) 620–625