PATMOS 1996 157 CMOS Short-Circuit Power Dissipation Including Velocity Saturation and Gate-to-Drain Capacitive Coupling L. Bisdounis, S. Nikolaidis 1 , O. Koufopavlou VLSI Design Laboratory, Department of Electrical & Computer Engineering, University of Patras, 26500 Patras, GREECE 1 Electronics & Computers Division, Department of Physics, University of Thessaloniki, 54006 Thessaloniki, GREECE E-mail: bisdouni@ee.upatras.gr ABSTRACT In this paper an accurate analytical model for the evaluation of the CMOS short-circuit power dissipation, on the basis of a CMOS inverter, is presented. The innovation of the proposed approach against previous works is due to the accurate, analytical expressions of the inverter output waveform which include for the first time the influences of both transistor currents, and the gate-to-drain coupling capacitance. The -power law MOS model which considers the carriers velocity saturation effects of short-channel devices, is used. The results produced by the suggested model show good agreement with SPICE simulations. I. INTRODUCTION Since, power dissipation is one of the most critical parameters in VLSI circuits [1], accurate and efficient power evaluation during the design phase is required in order to meet the power specifications without a costly redesign process. Power dissipation in CMOS circuits consists mainly of two parts, the dynamic and the short-circuit power dissipation. Dynamic dissipation caused by charging and discharging the load capacitance is well understood and easy to be estimated. During the input transition in a static CMOS structure, a direct path from power supply to ground is caused, resulting to short-circuit power dissipation. The emphasis of this work is on evaluating analytically, the short-circuit power dissipation of a CMOS inverter. To do this, analytical expressions of the output waveform, for the operation regions where short-circuit current exists, must be derived. Analytical expressions for the output waveform including the input slope effects was presented in [2], [3], where the influence of the short-circuit current was neglected. These works are based on the Shichman- Hodges square-law MOS model [4] that ignores the carrier velocity saturation effect. Jeppson [5] presented expressions of the inverter output waveform considering the currents through both transistors, but still based on the square-law MOS model. Sakurai and Newton [6], [7] introduced the -power (n-power in [7]) law MOS model that considers of the velocity saturation effect, which becomes prominent in short-channel devices, and they presented analytical expressions for the inverter output waveform. However, in [6] the short-circuit current is neglected, while in [7] a fictitious input ramp is used in order to approximate the