The ARISE Reconfigurable Instruction Set Extensions Framework Nikolaos Vassiliadis, George Theodoridis, and Spiridon Nikolaidis Sect. of Electronics & Computers, Depart. of Physics Aristotle University of Thessaloniki Thessaloniki, Greece e-mail: nivas@physics.auth.gr Abstract—In this paper, we introduce the ARISE framework for the systematic extension of typical processors with the necessary infrastructure to support arbitrary number and type of reconfigurable hardware units. ARISE extends the micro- architecture of the processor with an interface to allow the coupling of the hardware units. Furthermore, the instruction set of the processor is extended with instructions which expose to the programmer/compiler the full control of the interface. This control includes the configuration of operations on the hardware units, execution of these operations, and communication of data between the processor and the units. The new instructions are incorporated without the need to redesign the processor instruction set architecture. To evaluate our proposal a model of an ARISE extended MIPS processor has been designed. Using a turbodecoder algorithm as benchmarking application a simulation of the ARISE model has been performed. Performance results show impressive application speedups up to x7.5. I. INTRODUCTION Instruction set customization is an effective way to improve performance over a certain set of applications (application domain). Critical portions of the application can be more efficiently executed on Custom Computing Units (CCUs). While the base instruction set serves as the bulk of the flexibility used to implement any application, the customized instructions utilize the CCUs to enhance performance over the target application domain. Furthermore, providing to the CCUs the capability to reconfigure their functionality, high degrees of flexibility are gained. Reconfigurable units provide dynamic instruction set extensions offering the adaptation of the system to the targeted application. The process of designing such a hybrid system, except from designing the CCUs itself, is divided in two steps: first provide an interface between the processor and the CCUs and second expose to the architecture the control of the new system. Although a number of such systems have been presented in the literature most of them use an ad-hoc design approach to couple the CCUs to the processor. In addition, most systems are designed based on the needs of the attached CCUs excluding this way modularity and making difficult the extension of the system with new types of CCUs. Finally, in most cases the approaches presented in the literature are suffering from limitations which could reduce performance. Such limitations are the number of parameters which the CCU can access (parameters limitation), the opcode space available to encode operations performed in the CCUs (opcode space explosion) etc. In this paper we present the AUTH Reconfigurable Instruction Set Extension (ARISE) framework. The framework extends a typical processor with: 1) a micro-architectural interface which is used to couple CCUs to the processor and 2) a set of instruction set extensions to control the interface. These extensions are one-time performed to a processor to create an ARISE machine. After that, an arbitrary number of CCUs can be attached to the machine. Moreover, the CCUs complexity can vary from hardwired to reconfigurable units with multiple contexts of configurations. The instruction set extensions exposes to the programmer/compiler all necessary instructions required to control the configuration of operations in the CCUs, their execution, and the communication of arguments between CCUs and the processor. Furthermore, using a buffering technique ARISE overcomes the parameters limitation while exploiting at the same time the complete register file bandwidth. ARISE also deals with the opcode space explosion by dynamically assigning opcodes to operations. To evaluate the proposal, a model of an ARISE extended MIPS processor was designed. A turbodecoder application was implemented in the ARISE machine and simulations was performed to estimate the performance of the machine and identify any possible bottlenecks. Results indicate that the ARISE machine is able to speedup the execution of the application by a factor of 7.5. The rest of the paper is organized as follows. Section II gives a general description of the ARISE framework and discusses in detail the general organization of an ARISE machine, the ARISE micro-architectural interface and the ARISE instruction set extensions. Furthermore, the procedure which must be followed to program an ARISE machine is also described. Section III presents the design of an ARISE evaluation machine based on a MIPS core processor. Experimental results are presented in section IV. Section V discusses some related work while we conclude in Section VI.