A voltage-dependent channel length extraction method for MOSFET’s Mojtaba Joodaki * Qimonda AG (former Infineon Technologies AG), 81726 Munich, Bayern, Germany Received 4 July 2006; received in revised form 27 September 2006; accepted 30 September 2006 The review of this paper was arranged by Prof. S. Cristoloveanu Abstract In this paper a new method for extraction of the channel length and channel resistance as a function of gate-voltage in MOSFET’s is introduced. The method is accurate and calculates the threshold voltages of all devices with different gate-lengths. The channel resistance is divided in two parts; the first part is a function of gate-voltage and threshold voltage difference (V g  V t ) and the second part is only a function of gate-voltage. Further, the model determines the threshold voltage of short-channel devices independent of their parasitic resistances and implements the channel mobility as an arbitrary function of gate-voltage while the gate-voltage-dependent part of the resistance is uniquely separated from the first part of channel resistance for all devices. Ó 2006 Elsevier Ltd. All rights reserved. Keywords: MOSFET’s; Channel length extraction; Drain–source resistance 1. Introduction The effective channel length (L eff ) and drain–source resistance (R ds ) of the MOSFET’s are of utmost impor- tance for circuit modeling, process monitoring and device design. There have been several attempts to extract the MOSFET’s channel length in the submicron region where many difficulties arise due to the strong variation of mobil- ity with gate-voltage, higher influence of graded source and drain doping profiles, and the lithography near to the opti- cal resolution limit [1–5]. Although most circuit models do not implement a gate-voltage-dependent channel length, it is known that both the channel length reduction parameter (DL = L mask  L eff , where L mask is the design length on the polysilicon etch mask and in this paper is referred to as ‘‘gate-length’’) and the drain–source resistance vary with gate-voltage [2]. That is why this paper focuses on extract- ing the gate-voltage-dependent channel length reduction parameter and the channel resistances for different gate regions while the constant part of the drain–source resis- tance is uniquely separated from the voltage-dependent drain–source and channel resistances. The proposed method is described in the next section and the verification results are presented in Section 3. 1.1. The proposed method The basic principles of this approach are similar to those of the improved ‘‘shift and ratio’’ method [5,6] but in addi- tion to the short and long channel devices a reference device, which is the second longest device, is required. Fur- ther, in the new method differentiation of the externally measured total resistance (R tot ) is avoided, which prevents the large errors arising from measurements noises at low gate-voltage ranges. Kwong et al. presented a method [7] in which three devices with different gate-lengths are implemented. In their model they assumed that the drain–source resistance can be ignored in the long channel device in comparison with the channel resistance and minimized the mean-square 0038-1101/$ - see front matter Ó 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2006.09.020 * Tel.: +49 89 234 45912; fax: +49 89 234 9551891. E-mail address: mojtaba.joodaki@qimonda.com www.elsevier.com/locate/sse Solid-State Electronics 50 (2006) 1787–1795