Energy-Aware Network-on-Chip Application Mapping Based on Domain Knowledge Genetic Algorithm Yin Zhen Tei 1 , Yuan Wen Hau 2 , N. Shaikh-Husin 1 , Trias Andromeda 3 , M. N. Marsono 1 1 Department of Electronic and Computer Engineering, Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Johor, Malaysia. 2 IJN-UTM Cardiovascular Engineering Center, Faculty of Biosciences and Medical Engineering, Universiti Teknologi Malaysia, Johor, Malaysia. 3 Department of Electrical Engineering, Diponegoro University, Semarang, Indonesia. Email: yztei2@live.utm.my, hauyuanwen@biomedical.utm.my, nasirsh@fke.utm.my, triasandromeda@undip.ac.id, nadzir@fke.utm.my Abstract—This paper addresses energy-aware application mapping for large-scale Network-on-chip (NoC). The increasing number of intellectual property (IP) cores in multi-processor system-on-chips (MPSoCs) makes NoC application mapping more challenging to find optimum core-to-topology mapping. This paper proposes an application mapping technique that incorporates domain knowledge into genetic algorithm (GA) to minimize the energy consumption of NoC communication. The GA is initialized with knowledge on network partition whereas the genetic crossover operator is guided with inter-core communication demands. NoC energy estimation is based on analytical energy model and cycle-accurate Noxim simulation. For large-scale NoC, application mapping using knowledge-based genetic operator saves up to 28% energy compared to the one on conventional GA. Adding knowledge-based initial mapping speeds up convergence by 81% and further saves energy by 5% compared to only knowledge-based crossover GA. Furthermore, cycle-accurate simulations of applications with traffic dependency show the effectiveness of the proposed application mapping for large-scale NoC. Keywords—Application mapping, bit energy model, cycle- accurate simulation, domain knowledge, genetic algorithm, network-on-chip I. INTRODUCTION Network-on-chip (NoC) has emerged as a promising on- chip communication architecture providing modularity and scalability for multi-processor System-on-Chips (MPSoCs). Application mapping determines the placement of intellectual property (IP) cores to routers on NoC tiles such that the performance or cost metrics of interest are optimized [1]. Large MPSoC requires an effective mapping algorithm to reduce the large search space to obtain optimum mapping. Domain-knowledge has been used in crossover and mutation operators to improve GA mapping and convergence [2] by checking each gene’s communicating distances with other cores. However, this increases computation time drastically for highly communicating applications and large- scale NoCs. Large-scale MPSoCs are mostly combinations of several subsystems. Network partitioning (NP) can be utilized to narrow down application mapping search space. Analytical energy models commonly used in application mapping are bit energy model [3] and communication cost [4]. Both analytical models are hop-count based that offer fast cost or performance estimation. Cycle-accurate simulation gives more accurate estimation but is time consuming. Thus, it is important to analyse NoC energy accurately to obtain mapping with minimum energy. The accuracy of cost and performance estimation is equally important especially during NoC design stage. This paper proposes an application mapping technique that incorporates domain knowledge into genetic algorithm (NP- DKGA) to minimize the energy consumption of NoC communication. NP-DKGA operates in two phases: network partitioning knowledge as initial population; and knowledge- based crossover to search for near optimum mapping. This technique is verified with several benchmarks. The proposed energy-aware application mapping is verified with both analytical energy model and cycle-accurate simulation using Noxim [5]. With only knowledge-based crossover, the GA converges well for all small communicating benchmarks. For highly communicating benchmarks, knowledge-based initial mapping can further optimize energy consumption and speeds up the GA convergence. The rest of this paper is organized as follows. Section II discusses related works mainly on crossover and partitioning in application mapping. Section III presents the proposed application mapping technique based on the combination of knowledge-based initial mapping and crossover in GA as well as their formal definitions. Section IV discusses the simulation tools and parameters. Section V discusses the experiment results. Finally, Section VI concludes the paper and presents suggestion for future works. Corresponding author: M. N. Marsono, nadzir@fke.utm.my Proceeding of International Conference on Electrical Engineering, Computer Science and Informatics (EECSI 2014), Yogyakarta, Indonesia, 20-21 August 2014 86