FPGA IMPLEMENTATION AND ANALYSIS OF A MULTILEVEL CODED MODULATION SCHEME M. Albanese, I. Rinaldi, and A. Spalvieri, Dipartimento di Elettronica e Informazione, Politecnico di Milano, Piazza Leonardo da Vinci, 32, I-20133 Milano (Italy), albanese,irinaldi,spalvier @elet.polimi.it Abstract - The authors describe a multilevel coded modula- tion scheme that has been designed for being implemented on FPGA. The goal of the design is to obtain good performance while keeping decoding delay and computational complexity as low as possible. This goal is obtained by a two-level scheme, where the partition chain of the 8-dimensional Gosset lattice is associated to a combination of 16-ary convolutional and block codes, at the first and second level respectively. The motivations behind the design choices are illustrated and the implementation on FPGA is presented. The authors conclude by analyzing the performance of the system and by showing experimental results. Keywords - Multilevel Coded Modulation, Reed-Solomon Codes, Ordered Statistics Decoding. I. INTRODUCTION It has been shown [1, 2] that multilevel codes (MLC) com- bined with staged decoding can reach high coding gain and reduce decoding complexity with respect to Maximum Like- lihood (ML) decoding. Nevertheless, staged decoding of the outer codes may increase both storage requirements and sys- tem delay. These parameters cannot be ignored when the coded scheme has to be implemented. To cope with these practical requirements we propose a two-level scheme where the length of the outer codes is kept as small as possible. A careful choice of the outer codes and of the inner lattice is therefore necessary to obtain good performance. We present a scheme based on the Gosset lattice and its partition chain . The real code formulas of and are [3] where is the binary Reed Muller code of length , codewords, and minimum Hamming distance , is the binary parity check code of length , and is the binary repetition code of length . Choosing as top lat- tice allows for more accurate tentative decisions with respect to , thanks to the greater redundancy. Moreover, if com- pared to lower-dimensional lattices, leads to a reduction of the frequency of operation of the outer codes for a given frequency of the channel signal. The partitions and have order 16, so 16-ary outer codes are necessary. Block, convolutional codes, or a combination of them can be used. If block codes are adopted [4], Maximum-Distance- Separable (MDS) codes over GF(16), such as Reed-Solomon codes (RS) or extended versions of them, represent an attrac- tive solution. Yet, even sub-optimal decoding of 16-ary RS codes of rate near 1/2 is computationally too hard. An alter- native, at least at the first level, is represented by convolu- tional codes. Indeed, good convolutional codes over GF( ) that are optimal in terms of error probability for a given con- straint length are studied in [5]. Furthermore, various tech- niques have been described for efficient design of the Viterbi Algorithm [6, 7, 8], which is the classical algorithm for ML decoding of convolutional codes. These techniques originally apply to binary codes but some of them can be extended to codes with an arbitrary alphabet. At the second level a higher rate code may be obtained by puncturing the first level con- volutional code. We prefer to adopt a combination of convo- lutional and block codes. More precisely, we use a rate-1/2 convolutional code at the first level and the singly-extended Reed-Solomon code seRS(16,14) at the second level. Actu- ally, short high RS codes with high rate are well suited for be- ing decoded using a suboptimal decoding algorithm derived from [9]. We show that this algorithm achieves practically optimum performance and that it allows to use about 1/5 of the total area with respect to ML decoding of the same code or ML decoding of a punctured convolutional code of similar rate and performance. The multilevel system just described has been implemented on an Altera APEX20KE device. In Section 2 we briefly describe the system implementation. In Section 3, the performance of our scheme is analyzed and ex- periemental results are illustrated. Conclusions are drawn in Section 4. II. SYSTEM IMPLEMENTATION Implementation of the encoder is straightforward, and details about it are therefore skipped. The staged decoder depicted in figure 1 is composed by The lattice decoder, that returns the metrics for the GF(16) symbols at the first and second level; The Viterbi decoder for the rate-1/2 convolutional code 0-7803-7589-0/02/$17.00 ©2002 IEEE PIMRC 2002