> MNS-568 < 1 Abstract— The explosion of the telecommunications market requires miniaturization and cost-effective realization of the front-ends of transceivers for digital telecommunications. New architectures must therefore be simulated at high level. Current methodologies and corresponding tools suffer from common drawbacks, such as lower accuracy, slow simulation speed, etc. A new methodology has been developed for the efficient simulation, at the architectural level, of mixed-signal front-ends of digital telecom transceivers. The efficient execution is obtained using a multi-rate, multi-carrier signal representation together with a dataflow simulation scheme that switches dynamically to the most efficient signal processing technique available. An implementation of this methodology shows both excellent runtimes and a high accuracy for realistic front-end architectures. Index Terms—Circuit simulation, Communication systems, Design automation, Signal representations. I. INTRODUCTION ith the explosion of the telecommunications market there is a strong pressure towards miniaturization and cost-effective realization of the front-ends of transceivers for digital telecommunications. This requires a study of new architectures. For such studies and in order to determine the specifications of front-end blocks, high-level simulation is preferred over rough hand calculations, since a much higher accuracy can be obtained. During the architectural design of the digital blocks of a telecom transceiver, the performance of the complete telecom link is often measured with bit-error-rate (BER) simulations. An optimal design of a complete transceiver requires simulations that take into account the signal degradations caused by the analog front-end blocks. Analog blocks are most often simulated at the transistor level. However, this Manuscript received October 9, 2000, revised March 25, 2002. This work was supported in part by the Flemish IWT and by the EEC ESPRIT program in the framework of the Low-power design cluster, which is coordinated by DIMES, Delft, the Netherlands. Piet Wambacq, Gerd Vandersteen, Petr Dobrovolný, Michael Goffioul and Stéphane Donnay are with IMEC, B-3001 Heverlee, Belgium. Yves Rolain is with the department ELEC of the Vrije Universiteit Brussel, Belgium. high level of detail yields a low simulation efficiency compared to the digital blocks, which are most often simulated at a higher level. The simulation efficiency improves if the analog blocks are simulated at a higher abstraction level with dedicated simulation techniques. This paper describes such technique. Efficient numerical computations can take advantage of the technique of vector processing [1, 2], which handles data at different timepoints in large vectors instead of processing single data points. This makes it possible to take full advantage of the capabilities of the processor, as is done for example in MATLAB [1]. This technique is useful for front- end simulations at the architectural level, as long as the architectures do not contain any feedback. Although front- ends in essence are feedforward structures, they can contain several feedback paths, which is the case e.g. with a phase- locked loop or an automatic gain control. In feedback loops the signals need to be calculated on a timepoint-by-timepoint or sample-by-sample basis. This approach is far less efficient than vector processing. The most straightforward technique to simulate analog front-ends that contain RF circuits as well as baseband circuits is a SPICE-like time-domain simulation approach that solves a set of nonlinear differential equations with numerical integration (using a non-equidistant timestep). This approach is not efficient for wireless systems where RF frequencies are in the GHz range and the baseband frequencies in the MHz or even in the kHz range. Indeed, this approach requires a timestep that is small enough in order not to introduce aliasing by the sampling of the waveforms. In this way the timestep is upper bounded by the RF signals and lower bounded by the period of the lowest frequency in the simulation. This yields very long simulation times. A harmonic balance approach does not suffer from this large difference of frequencies and it is sometimes used for system-level simulations of analog front-ends [3]. However, harmonic balance methods are only good at simulating nonlinear circuits with periodic signals that can be described by a small number of sinusoidal tones and their harmonics. A digitally modulated signal, however, cannot be represented accurately in this way. Dataflow simulation of mixed-signal communication circuits using a local multirate, multicarrier signal representation Piet Wambacq, Member IEEE, Gerd Vandersteen, Member IEEE , Yves Rolain, Member IEEE , Petr Dobrovolný, Michael Goffioul, Stéphane Donnay, Member IEEE W