JOURNAL OF ELECTRONIC TESTING: Theory and Applications 22, 11–22, 2006 c  2006 Springer Science + Business Media, Inc. Manufactured in The United States. DOI: 10.1007/s10836-006-4835-z Scaling of i DDT Test Methods for Random Logic Circuits ALI CHEHAB American University of Beirut, Beirut, Lebanon chehab@aub.edu.lb SAURABH PATEL University of North Carolina at Charlotte, Charlotte, NC 28223, USA RAFIC MAKKI College of Information Technology, UAE University, AL-Ain, UAE makki@uaeu.ac.ae Received December 21, 2003; Revised September 7, 2005 Editor: Z Li Abstract. We present a scaling methodology to improve i DDT fault coverage in random logic circuits. The study targets two i DDT test methods: Double Threshold i DDT and Delayed i DDT . The effectiveness of the scaling methodology is assessed through physical test measurements, and studied relative to process variation and impact on circuit performance. The scaling is made possible using a clustering methodology that can significantly improve fault coverage. The results show that without clustering, the effectiveness of the i DDT testing methods considered is greatly reduced as the circuit size increases. Keywords: dynamic power supply current, design for current testability, resistive opens, resistive bridges, fault simulation, very deep sub-micron technologies, VDSM 1. Introduction Recent i DDT research has shown potential for i DDT testing to augment traditional test methods and increase fault cov- erage. Simulation results have shown that i DDT can success- fully detect floating gate defects, source/drain open defects [13, 24], as well as cell transition and coupling faults in SRAM’s [11]. In a recent study, the transient response is ana- lyzed in the time domain at distributed measurement points [6, 18, 19]. In [20], the transient response is transformed into the frequency domain where correlation and regres- sion analysis are performed; the transient signal analysis method incurs increased measurement and computational complexity due to multiple test point measurements. Other researchers proposed to determine the average value of the transient current to successfully detect stuck-open defects [15]. Studies have also shown that the Energy Consump- tion Ratio, ECR, [2, 27] can be used to detect defects. This method performs average current measurements of a num- ber of sequences and computes the corresponding ECRs. Each ECR has a corresponding pre-computed good circuit average. The ECR is process tolerant; however, one aspect of this method is the increased test time due to large number of applied test vector pairs. Also increased leakage currents in today’s circuits affect the average current and limit the effectiveness of the test. Statistical formulation of thresh- olds for i DDT is proposed in [7]. In [21], a technique is proposed that is based on the golden signature of the DUT and whereby one sample of i DD is taken per test vector at a predetermined instance. In [8], a hardware solution of an i DDT monitor is presented that allows real-time testing for 0.25 micron CMOS devices. In [23] a method is presented that is based on measuring and computing the charge deliv- ered during the transient operation. In this technique the area under two different waveforms, one for a good circuit and another for a defective circuit, may lead to very close results even though one circuit is defective. Also, similarly to ECR, its resolution reduces with very large values of leakage. In [28] a method is proposed based on the fact that some open defects cause delay faults and that such faults will cause i DDT to have a delayed peak, and a longer duration. By set- ting the observation window past the good circuit transition