Characterization of a High-Q On-Chip Transmission Line for CMOS MMIC Applications M. Fahimnia*, M. Mohammad-Taheri**, B. Biglarbeigian***, S. Safavi-Naeini**** University of Waterloo, mfahimni@maxwell.uwaterloo.ca* University of Tehran, mtaheri@ut.ac.ir** University of Waterloo, bbiglarb@maxwell.uwaterloo.ca *** University of Waterloo, safavi@maxwell.uwaterloo.ca**** Abstract: A high quality factor transmission line structure with shielded ground plane and curved side-walls is proposed for CMOS MMIC applications. The structure is optimized, fabricated and characterized up to 40 GHz. Instead of conventional open, short and thru de-embedding methods which occupies a large chip area, a simple yet accurate de-embedding method using lines with different lengths is employed. Simulated and measured data are compared which shows are in good agreement. The extracted line parameters are studied and it is seen that even with the shielded ground; the quality factor of the line degrades at very high frequency due to the substrate loss. Keywords: Transmission line (TL), Microwave integrated circuit (MMIC), CMOS, Q (quality factor). 1. Introduction CMOS/SiGe technologies are promising for low cost MMIC based systems [1-5]. Other than high frequency transistors, high quality passive elements are needed to realize circuit building blocks for these systems. Low resistive silicon substrate which is required for active elements deteriorates quality factor of passive elements [3-6]. As the frequency increases, more loss mechanism taking into place and further increase signal attenuation in CMOS/SiGe passive elements. High performance transmission lines are required to provide low loss interconnection and to replace bulky and lossy inductors in MMIC. TLs have also broad band characteristics and are easier to model [5]. Usually coplanar waveguide (CPW) is used in RF circuits for this purpose. However, as frequency goes higher, CPW suffers from high substrate loss [6-7]. This is due to the thin dielectric layer in CMOS back end of line (BEOL) which is in order of a few microns. Thus, the field lines penetrate into the silicon lossy substrate and deteriorate the quality factor of the line [6]. To alleviate this problem, grounded CPW (GCPW) is proposed for microwave frequencies [4-7]. Using the bottom thin metal layer of the BEOL, a mesh grid is utilized to shield the signal from the lossy silicon substrate. Mesh structure is implemented in order to meet the metal density requirements for reliable fabrication process as a part of density design rules. However, GCPW structure requires a large gap between signal and ground plane which makes it difficult to be implemented in the presence of metal density rules and also occupy the expensive chip area [6]. In comparison, microstrip structures if properly designed provide higher quality factor, inductance per lengths and lower size which makes them suitable for MMIC applications. In this paper, a TL structure, which is suitable for MMIC in CMOS/SiGe technologies, is presented in section 2. Instead of conventional open, short and thru de- embedding methods [8-11] which occupies a large chip area, a simple yet accurate de-embedding method using two lines with different lengths is employed. The lines are characterized up to 40 GHz and line parameters are derived and verified with measurement. 2. On-chip TL Structure Simplified proposed TL structure is shown in Fig. 1. (a) (b) Fig. 1: (a) Simplified structure and (b) cross-section of the TL