Field Programmable Multi Chip Modules using Programmable Laser Interconnects Vikram Pasham, Wilfrido A. Moreno, Fernando J. Falquez Center for Microelectronics Research University of South Florida 4202 E. Fowler Ave., Tampa, FL 33620, USA. Phone: (813) 974-4775, Fax: (813) 974-5250 Email: moreno@eng.usf.edu Abstract Researchers have been performing extensive studies in Multi-FPGA systems for rapid prototyping, logic emulators, reconfigurable computing and software accelerators. Traditional prototyping systems mapped on to multi-FPGA systems have considerable delay and do not reflect the actual timing characteristics of the custom design. An innovative methodology is proposed for prototyping and also for implementation of the design using FPMCM. Two types of FPMCM are used, i.e. SRAM based FPMCM and Laser Vertical Link (LVL) [1] based FPMCMs. This proposed FPMCM systems have better performance characteristics than the conventional multi-FPGA systems due to the inherent advantages of MCMs over PCB systems coupled with faster programmable interconnects. 1 Introduction Many methods are formulated to accelerate the ASIC design cycle time. As the industry adheres to the Moore’s Law, electronic products are becoming obsolete with each semiconductor generation. Obviously decreasing product life cycle means an ever- increasing need to reduce development time. Thus, time to market is increasingly more crucial factor in achieving the competitive edge and this is achieved to a large extend by FPGAs. If a product in particular algorithm has to be implemented in hardware, then these FPGAs form a perfect platform. The validation of the circuit is performed either by using Software simulation or Test Prototyping of the circuit. With the increase in the complexity of the chip, software simulation became inaccurate and some simulations never converge or take long time to converge. Prototype fabrications were also not economically feasible for complex circuits, as they are very expensive both in cost and time. Using FPGAs for logic emulation eliminates these intermediate steps. Logic emulation takes much less time compared to software simulation and also this is more flexible than prototype fabrication. The verification is an iterative process, improving the design with each iteration and the reprogrammability of FPGA suites this process. After verification the next step is to implement the circuit using either custom layout or mapping on to FPGA system. These FPGAs are fully tested after fabrication, and the designer need not test the final product, thus a major step in design cycle is eliminated. The ever-growing design complexity made it impossible to map the complete design into a single FPGA. FPGAs with 100k gates are available in the market, but still they do not cater to highly complex designs like Encoding for gigabit Ethernet routers, Voice encoders [4], [8] etc. To overcome this hurdle complex designs are partitioned and mapped on to multi-FPGA placed on a PCB board. The drawback of these multi-FPGA systems was that they were too slow due to the off-chip delay on the PCB board. Joel and his group developed FPMCM [2] with FPGA dies placed on a MCM and the inter-routing between the dies was carried out using Aptix’s SRAM based Field Programmable Interconnect (FPIC). From now on FPGA dies will be referred as Field Programmable Logic Devices (FPLD). We propose to use two types of multi-FPLD systems, one for prototyping and the other for actual implementation i.e. SRAM based multi FPLDs and LVL based multi FPLD systems. The SRAM based multi-FPLDs are more suitable for rapid prototyping, as their reprogrammability suites for logic emulation. However SRAM based FPMCM have some delay associated and they cannot match LVL- FPMCM in