A Tool for Signal Probability Analysis of FPGA-Based Systems Cinzia Bernardeschi 1 , Luca Cassano 1 , Andrea Domenici 1 and Paolo Masci 2 1 Department of Information Engineering, University of Pisa, Italy 2 Department of Electronic Engineering and Computer Science, Queen Mary University of London, United Kingdom Email: {cinzia.bernardeschi, luca.cassano, andrea.domenici}@ing.unipi.it, paolo.masci@eecs.qmul.ac.uk Abstract—We describe a model of Field Programmable Gate Array based systems realised with the Stochastic Activity Net- works formalism. The model can be used (i) to debug the circuit design synthesised from the high level description of the system, and (ii) to calculate the signal probabilities and transition densities of the circuit design, which are parameters that can be used for reliability analysis, power consumption estimation and pseudo random testing. We validate the developed model by reproducing the results presented in other studies for some representative combinatorial circuits, and we explore the applicability of the proposed model in the analysis of real-world devices by analysing the actual implementation of a circuit for the generation of Cyclic Redundancy Check codes. Keywords-FPGA, Signal Probability, Simulation, Transition Density. I. I NTRODUCTION AND RELATED WORKS Field Programmable Gate Array (FPGA) devices are widely used components in many different application fields, includ- ing safety-critical systems. Especially in embedded and mobile applications, the assessment of such quality factors as power consumption and reliability is of fundamental importance. It has been shown that these factors may be estimated in terms of signal probability [1], [2], [3], [4], that can be defined as the fraction of clock cycles in which a given signal is high [5]. Another useful parameter is transition density, i.e., the fraction of clock cycles in which a signal makes a transition [6]. Other applications of signal probabilities are soft error rate estimation [7] and random testing [8]. Soft error rate is the error rate due to Single Event Upsets, i.e., errors caused by radiations, that are a major threat to system reliability. In random testing, test patterns are generated at random to cover as many as possible fault modes of the system. The statistical distribution of the test patterns may be weighted according to the input signal probabilities to optimise the coverage. The computation of signal probabilities may rely on either an analytical or a simulative approach. With analytical models, exact values of signal probabilities can be computed, but the computation is NP-hard in the general case [9], so it is usually necessary to resort to heuristic approximations. With a simulative approach, a model of the system is fed with inputs whose values reflect the expected statistical properties, and the simulated output signals are recorded and analysed to evaluate the resulting properties. In this paper, we present a model of FPGA circuit execution that can be used to calculate the signal probabilities and transition densities of a given FPGA design, starting from the signal probabilities of the inputs. The model is based on the formalism of Stochastic Activity Networks (SAN) [10] and it has been developed with the M¨ obius tool [11]. In FPGA systems, a high-level design is implemented with the configurable logic blocks made available by a given FPGA chip. In order to attain a realistic model and satisfactory accuracy of the analysis, the proposed model represents the FPGA system at this implementation level. The model is implemented by a simulator that takes as input a description of the system to be simulated and a few configuration parameters, including the signal probabilities of the inputs, the number of simulated clock cycles etc. The simulator generates input vectors according to the specified signal probabilities of the inputs and the results are collected and analysed using the features of the underlying M¨ obius environment. In the rest of this paper, the FPGA technology (Section II) and the SAN formalism (Section III) are introduced, then the formal model of FPGA circuit execution is presented (Section IV) and a case study is shown as a proof of concept (Section V). Conclusions and future work are in Section VI. II. THE FPGA TECHNOLOGY An FPGA is an array of programmable logic blocks, inter- connected through a programmable routing architecture and communicating with the output through programmable I/O pads [12]. The programming of an FPGA device consists in downloading a programming code, called bitstream, in its configuration memory, that determines the hardware structure of the system to be implemented in the FPGA, and thus the functionality performed by the system. The logic blocks may be simple combinatorial/sequential functions, such as lookup tables, multiplexers and flip-flops, or more complex structures such as memories, adders, and micro- controllers. The routing architecture in an FPGA consists of wires and programmable switches that form the desired connections among logic blocks and I/O pads. Finally, the I/O architecture is composed of I/O pads disposed along the perimeter of the device, each one implementing one or more communication standards. An FPGA system is described at the Register-Transfer Level (RTL) in terms of high-level registers and logic functions, independent of their implementation on a particular device. 13 COMPUTATION TOOLS 2011 : The Second International Conference on Computational Logics, Algebras, Programming, Tools, and Benchmarking Copyright (c) IARIA, 2011. ISBN: 978-1-61208-159-5