LCF-style for Secure Verification Platform based on Multiway Decision Graphs Sa’ed Abed 1 and Otmane Ait Mohamed 2 1 Department of Computer Engineering, Hashemite University, Zarqa, Jordan sabed@hu.edu.jo 2 Department of Electrical and Computer Engineering, Concordia University, Montreal, Canada ait@ece.concordia.ca Abstract. Formal verification of digital systems is achieved, today, us- ing one of two main approaches: states exploration (mainly model check- ing and equivalence checking) or deductive reasoning (theorem proving). Indeed, the combination of the two approaches, states exploration and deductive reasoning promises to overcome the limitation and to enhance the capabilities of each. A comparison between both categories is dis- cussed in details. In this paper, we are interested in presenting as an example a platform for Multiway Decision Graphs (MDGs) in LCF-style theorem prover. Based on this platform, many conversions such as the reachability analysis and reduction techniques can be implemented that uses the MDG theory within the HOL theorem prover. The paper also questions the best formalization principle of decision graphs to build such a platform in theorem proving since a set of basic operations are used to efficiently manipulate the decision graphs which constitute the kernel of the model checking algorithms, by describing two alternatives to formalize these decision graphs. Then we contrast between them ac- cording to their efficiency, complexity and feasibility. Finally, we hope this paper to serve as an adequate introduction to the concepts involved in formalization and a survey of relevant work. 1 Introduction With the increasing complexity of the design of digital systems and the size of the circuits in VLSI technology, the role of design verification has gained a lot of importance. Serious design errors and bugs take a lot of time and effort to be detected and corrected especially when they are discovered late in the verification process. This will increase the total cost of the chip. In order to overcome these limitations, formal verification techniques arose as a complement to simulation for detecting errors as early as possible, thus ensuring the correctness of the design. Formal verification of digital systems is achieved, today, using one of two main approaches: states exploration [29] (mainly model checking and equivalence