J Supercomput (2012) 59:22–41 DOI 10.1007/s11227-010-0413-3 MorphoSys reconfigurable hardware for cryptography: the twofish case Sohaib Majzoub · Hassan Diab Published online: 12 March 2010 © Springer Science+Business Media, LLC 2010 Abstract This paper presents the mapping and performance analysis of the Twofish algorithm on MorphoSys. MorphoSys is a reconfigurable architecture that can pro- vide high performance compared to custom hardware and yet preserves a level of flexibility compared to general-purpose processors. With today’s high demand for se- cure data transfer mediums including wired and wireless networks, there is a growing demand for real-time implementation of cryptographic algorithms. The choice of the Twofish algorithm, one of the five AES finalists, is because it is computationally in- tensive algorithm. It requires lookup tables, logical and arithmetic computations that stipulate high flexibility and performance. So it is a perfect algorithm to be mapped in order to evaluate such hardware. Keywords AES finalists · Cryptography · Decryption · Encryption · Key schedule · MorphoSys · Reconfigurable systems · S -box · Twofish algorithm 1 Introduction General-purpose processor (GPP) is a confined hardware system that computes any task using existing instructions and registers. Thus, GPP is used to compute diverse range of applications using its wide applicability. Application Specific Integrated Circuits (ASIC), on the other hand, are used to implement a single fixed function. Therefore, ASICs have no flexibility and they can only execute a very limited type of applications known before beforehand during fabrication. S. Majzoub ( ) · H. Diab Department of Electrical and Computer Eng’g, Faculty of Engineering and Architecture, American University of Beirut, P.O. Box 11-0236, Beirut, Lebanon e-mail: Sohaib.majzoub@ieee.org H. Diab e-mail: diab@aub.edu.lb