Variability Aware Performance Evaluation of Low Power SRAM Cell Hansel Dsilva, Julian Pinto, Arzan Elchidana and Sudhakar Mande Department of Electronics and Telecommunication, Don Bosco Institute of Technology, Mumbai University, India. email: dsilvahansel@ieee.org Abstract— Till today CMOS scaling is considered as the best option to achieve higher density, high performance and low power integrated circuits. However, scaling of con- ventional planar MOSFET in the sub-45nm regime leads to many undesirable short channel effects. FinFET is con- sidered as the suitable candidate for the replacement of conventional planar MOSFETs. In this work, suitability of FinFETs for replacement of planar bulk technology in sub- 20nm regime has been verified using Predictive Technology Models. For this purpose, the performance of the FinFET based SRAM cell is compared with conventional planar Bulk based SRAM cell. Moreover, robustness of FinFET based SRAM cell against process, temperature and power supply variations is evaluated and compared with conven- tional planar based SRAM cell. Our simulation results confirms the suitability of FinFETs for the replacement of conventional planar CMOS technology. Keywords—Predictive Technology Models,independent- gate FinFET based 6T SRAM, planar Bulk based 6T SRAM, PVT analysis, Static Noise Margin, Access Time. I. Introduction T HE impact of process variation on performance and yield of integrated circuits is emerging as one of the major problems for the continued CMOS scaling in the sub- 22nm regime. In order, to combat the variability in such aggressively scaled CMOS technology, research focuses on new device architectures. FinFET is considered as the most promising candidate for replacement of the conventional bulk MOSFET [1–3]. It is expected that ability of FinFET to be able to control the channel by its three sided gate configuration results in improvement in short channel performance and reduced variability. As compared to the planar Bulk device the FinFET device exhibits 100X greater I on /I off -ratio. In lit- erature, [4, 5] it is seen that the FinFET process flow is similar to that of a conventional Bulk device. For the emerging SRAM applications the FinFET plays a crucial role as it promises high noise margins and im- proved timings. In this work, FinFET application is fo- cused around SRAM cell as it is estimated to occupy nearly 90% of the chip area in the near future. But there exists area limitation in VLSI design. Hence, SRAM design needs to involve minimum sized devices which will provide at the same timings and equal stability as their large scale device based counterparts. As we approach the 22nm node for design of SRAM, we need to take into account device fluctuations induced due to random variations. In literature [4, 6], which focus on impact of process variations on the characteristics of the FinFET device. In this paper, impact of process, volt- age and temperature variations on SRAM performance is studied at the 16nm technology regime. The main reason behind including temperature variations is to see the im- pact of temperature inversion on the FinFET based SRAM. Also, the impact of supply voltage is studied to get a better idea of noise margin dependency on supply voltage. This will enable better definitions of design corners for sub-22nm FinFET technology. The models used for simulation were those developed by the PTM-group at Arizona State University. These mod- els are predictive and are designed in accordance to the ITRS- roadmap and are based on the BSIM-MG model. The PTM- group choose to target an I off = 0.1 nA/um for the PTM- CMG as given in [7,8]. To enable a compara- tive study between planar Bulk and FinFET technology, we have tuned the PTM-Bulk high-k 16nm model to I off = 0.1 nA/um. The rest of the paper is organized as follows. In the first section, we have characterized the FinFET based 6T SRAM cell at the 20nm, 16nm, 14nm, 10nm and 7nm technology nodes. The SRAM cell hold, read and write static noise margin followed by access timing was tabulated and a study was conducted to make predictions on the trend of the SRAM characteristics for further scaling beyond the 22nm technology node. In the second section, a comparative study between the PTM-Bulk high-k and PTM-CMG was conducted at the 16nm technology node. A study on the impact of beta-ratio on SRAM characteristics followed by a comparison with that of the PTM- Bulk high-k 16nm. This gives a more clear idea into the stability of the FinFET based SRAM cell and its advantages and disadvantages over the planar Bulk based SRAM. In the third section, variability analysis is explored by inducing process, voltage and temperature variation in the PTM-CMG and PTM-Bulk High K at 16nm technology node. This is summarized as seen in Fig.3 .This study will help in better understanding the yield of the FinFET based SRAM during fabrication. To the best knowledge of the authors, this is the first paper to include PVT-analysis of an FinFET based 6T-SRAM cell and compare the results to its counterpart planar Bulk based SRAM cell at 16nm technology node. 978-1-4799-1314-5/13/$31.00 ©2013 IEEE 183 5th Asia Symposium on Quality Electronic Design