Novel partially depleted SOI MOSFET for suppression floating-body effect: An embedded JFET structure Ali A. Orouji ⇑ , Abdollah Abbasi Electrical Engineering Department, Semnan University, Semnan, Iran article info Article history: Received 13 April 2012 Accepted 6 June 2012 Available online 15 June 2012 Keywords: Silicon-on-insulator Floating-body effect SiGe Simulation abstract Silicon-on-insulator (SOI) devices have an inherent floating body effect which may cause substantial influences in the performance of SOI devices and circuits. In this paper we propose a novel device structure to suppress the floating body effect by using an embed- ded junction field effect transistor (JFET). The key idea in this work is to provide a path for accumulated holes to flow out of the body to improving of electrical performance. We have introduced a p + -Si 1x Ge x buried region under the n + -Si 1x Ge x source and called the proposed structure as embedded JFET SOI MOSFET (EJFET– SOI). Using two-dimensional two-carrier simulation, the output and subthreshold characteristics of EJFET–SOI are compared with those of conventional SOI counterparts. The simulated results show the suppression of floating body effect in the EJFET–SOI structure as expected without consuming a significant amount of area. Ó 2012 Elsevier Ltd. All rights reserved. 1. Introduction Silicon on insulator (SOI) technology exhibits many advantages over bulk silicon technology such as the reduction of parasitic capacitances, excellent subthreshold slope, elimination of latch up, and resistance of radiation. It is widely used in realm of high-speed, high-temperature and low-power circuits. Partially depleted (PD) SOI devices are preferred to fully depleted (FD) ones, because the threshold voltage in PD SOI device is less sensitive to the uniformity in the silicon film thickness [1]. However, in a partially depleted (PD) SOI MOSFET, the bottom portion of the silicon film under the channel region is electrically floating. Hence, the floating body effect becomes an inherent issue in a PD SOI MOSFET [2]. This effect causes lowering of the drain breakdown voltage, kink effect [1], 0749-6036/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.spmi.2012.06.006 ⇑ Corresponding author. Tel.: +98 2614462954; fax: +98 2313331623. E-mail address: aliaorouji@ieee.org (A.A. Orouji). Superlattices and Microstructures 52 (2012) 552–559 Contents lists available at SciVerse ScienceDirect Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices