IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 8, AUGUST 2005 1839 A Study on Charge Reduction in HfO Gate Stacks Zhihong Zhang, Min Li, and Stephen A. Campbell Abstract—Charge in metal–organic chemical vapor deposi- tion-grown HfO gate stacks has been systematically studied using nMOS capacitors. It is found that, for these films, the charge in the stack is mainly concentrated at the interfaces between the layers and is negative at the HfO /interfacial layer (IL) interface and positive at the Si/IL interface. In general, the calculated charge densities at both interfaces are of order cm . A forming gas anneal (FGA) reduces both interface charge greatly. The FGA can also significantly reduce the hysteresis and interface state density. The effects of post deposition anneal at various temperatures and under various ambients have also been studied. It is found that a high-temperature dilute oxidizing ambient anneal followed by an FGA reduces the charge at both interfaces. Index Terms—Annealing, charge, gate stack, high- dielectrics, HfO , metal gate electrode, workfunction. I. INTRODUCTION M ANY reports exist in the literature of high permittivity materials and stacks for use as gate insulators [1]–[3]. The inversion layer mobility of these devices is almost invari- ably less than the universal curve [4], [5]. Thickening the in- terfacial layer seems to improve the mobility at the expense of decreasing the capacitance. It has been postulated that the mo- bility reduction is due to remote phonon scattering [5], but it is also well known that high- stacks have considerable charge and that this charge may also reduce mobility [6]. The charge may be formed during the high- deposition process, or during post de- position process steps. Metal-gate electrodes, for example, are of great interest to replace polysilicon for advanced MOS de- vices [2] since the Fermi level pinning at the polysilicon/metal oxide interface causes high threshold voltages [7], [8] and since metal gates may have the capability to reduce the effects of re- mote phonons [9], [10]. However, high-energy ions are often in- volved in metal gate deposition and patterning processes. This can induce charge in the high- stacks, making it difficult to ex- tract the charge information inherent in the high- stack itself. In this paper, we have used processes after the gate insulator deposition that have no energetic ion bombardment and studied the charge in HfO gate stacks as a function of forming gas an- neal (FGA) temperature and/or post deposition anneal (PDA) temperature and ambient. Manuscript received December 27, 2004; revised May 27, 2005. This work was supported in part by the Semiconductor Research Corporation under Con- tract 1060, and in part by the National Science Foundation through the National Nano Infrastructure Network (NNIN). The review of this paper was arranged by Editor G. Groeseneken. The authors are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA. Digital Object Identifier 10.1109/TED.2005.852729 II. EXPERIMENTAL MOS capacitors with a feature size of 100 100 m were formed on SiO and HfO gate dielectrics on p-type (100) Si. Control samples using SiO films were grown via thermal oxi- dation at 800 C for 20 min in dry O . Some of the SiO samples were then etched to the desired thickness using a 1:200 HF:H O solution. The HfO gate dielectrics were deposited via rapid thermal CVD [3] at 400 C using hafnium t-butoxide (HTB), i.e., Hf[(OC(CH )] , or HTB in combination with nitric oxide (NO). Ar was used as a carrier gas to deliver the HTB. The depo- sition was done on HF-last hydrogen terminated wafers with or without intentionally grown silicon oxynitride interfacial layer (IL). The physical thickness of the gate insulator was measured by ellipsometer. The predeposited ILs were grown at various temperatures in an Ultra High Vacuum (UHV) thermal oxynitridation system with NO as the feeding gas followed by a 935 C Ar an- neal in the same chamber. To minimize contamination, the chamber base pressure was maintained at torr. The thickness was measured with an 88-wavelength spectroscopic ellipsometer taking into account the interface roughness effect. After the IL layer formation and anneal, the wafer was in situ transferred to the MOCVD chamber to deposit HfO . To avoid all energetic processing, thermal evaporation was used for the gate metal deposition and wet chemical etching was used for patterning [11]. Although this restricts one to large geometries, the benefit is that one avoids any energetic bombardment of the insulator. After considerable study, it was found that Cr was a good candidate in that it did not appear to react with HfO . Cr has a much lower bonding energy with oxygen compared to that of Hf [12], suggesting that Cr is unlikely to reduce HfO . The Cr gated devices exhibited comparable interface charge to that of polysilicon gate devices we have made. Finally, as will be shown, the fact that Cr has a vacuum workfunction near the center of the silicon bandgap makes its effective workfunction less sensitive to the properties of the insulator. The PDAs were done for 10 s (unless otherwise specified) in a rapid thermal annealing system under various ambients and at various temperatures before gate deposition. The FGAs were done in 10%H /N at various temperatures for 30 min before gate deposition. Doing this avoids the potential for the gate electrode to act as a diffusion barrier to the H . All samples received backside Al metallization via thermal evaporation. Table I summarizes the sample processing history employed in this study. The capacitance–voltage (C–V) was measured using an HP 4294A precision impedance analyzer. The flat-band voltage and equivalent oxide thickness (EOT) were obtained using the NCSU CVC program [13]. The SiO samples were then used to extract the workfunction of the Cr gate materials. 0018-9383/$20.00 © 2005 IEEE