Improving performance of NEM relay logic circuits using integrated charge-boosting flip flop Ramakrishnan Venkatasubramanian *† , Sujan K. Manohar * and Poras T. Balsara * * VLSI Circuits and Systems Laboratory, University of Texas at Dallas, Richardson TX 75080 † Texas Instruments Inc, Dallas TX 75243 Email: {ramav, sujan.manohar, poras}@utdallas.edu Abstract—The zero leakage operation of Nano- electromechanical (NEM) relays has generated a lot of interest in low power logic design. Mechanical delay of the switches is orders of magnitude larger than the electrical delay and hence limits the speed of operation of NEM based digital logic circuits. The mechanical delay is inversely proportional to the gate-base voltage (V gb ). This paper presents an integrated voltage doubler based flip flop that improves the performance by 2X by overdriving V gb . The parallel plate capacitance between the gate and base of the relay is used to realize the storage capacitor for the doubler. It has been shown that for a flop fanout of 1, 2X performance boost could be achieved with 2X increase in area and 0.5X increase in power. For larger fanouts, the doubler is shared across multiple flops minimizing the area overhead. This approach can be extended as long as the overdrive does not create any reliability issues in the device. Accurate Verilog-A models were developed based on published fabrication results of scaled NEM relays [1] operating at 1V with a nominal air gap of 5 - 10nm. The area, power and performance trade-off for a sequential logic circuit with and without charge boosting is presented. I. I NTRODUCTION Nanoelectromechanical (NEM) Relays have an infinite sub- threshold slope similar to an ideal switch. They are 4 terminal devices similar to CMOS but are mechanical in nature and are electrostatically actuated. When the mechanical switch is turned ON, a metal channel creates a conducting path between source and drain. When the switch is OFF, there is no drain- source current and hence the leakage through the device is zero. The sub-threshold slope of CMOS and an ideal switch is shown in Fig. 1. NEM relay behaves like an ideal switch. The electrostatic actuation of the mechanical switch results in a mechanical delay through the relay, which is orders of mag- nitude more than the electrical delay of the logic implemented using the relays. Numerous NEM relay implementations have been proposed recently that show significant energy efficiency improvements over CMOS circuits while operating at low frequencies [1][2]. A cantilever beam based NEM relay has been reported in [3], which has been further improved to a suspended gate NEM relay in [1]. A laterally actuated NEM relay device is reported in [2] in which a poly-silicon beam is laterally actuated to realize the mechanical switch. Carbon-nanotube based NEM relays are reported in [5]. Even though this work is based on suspended gate NEM relays, the concept can be extended to any relay technology that provides parallel plate capacitances Fig. 1. Subthreshold slope definition which can act as storage capacitance for charge boosting. The speed of operation of NEM relay logic circuits is primarily limited by the mechanical delay of the relay. If t mon is the time taken to electrostatically actuate the relay, the theoretical maximum speed of operation of a NEM relay logic circuit is 1/2t mon . The mechanical delay (t m ) of a NEM relay is inversely proportional to the electrostatic potential applied between the gate and base terminals (|V gb |). Note that the relay turns ON whenever |V gb | crosses a certain threshold voltage (V pi ). This work proposes a scheme to overdrive V gb to improve the performance of the mechanical switch.Typically the relay device parameters would be optimized for a certain nomi- nal V gb overdrive voltage. Any additional overdrive voltage might result in device reliability issues. The localized charge boosting scheme proposed in this work can be used only if device reliability does not degrade significantly with the additional overdrive. There is lot of active research happening on improving the reliability of NEM relay devices. One such reported scheme is to apply an additional T iO 2 coating on tungsten electrodes of the device [1]. The parallel plate capacitance between the gate and base of the relay is significant enough and hence is used to realize the storage capacitance. The feasibility of localized charge boost- ing is tested out by integrating the charge-boosting logic into a NEM relay sequential cell. This concept can definitely be extended to other usage scenarios in NEM relay based circuit 37 978-1-4577-0995-1/11/$26.00 c 2011 IEEE