Structural Design Composition for C++ Hardware Models Frederic Doucet, Vivek Sinha, Rajesh Gupta Center for Embedded Computer Systems University of California at Irvine doucet,vsinha,rgupta @ics.uci.edu Abstract This paper addresses the modeling of layout structure in high level C++ models. Researchers agree that the level of abstraction for integrated circuit design needs to be raised. New languages and methodologies are being pro- posed, most of them influenced from the software engineer- ing domain. However, one of the fundamental hardware de- sign challenges is often overlooked as push button synthesis solutions are sought: physical design predictability. In this paper we describe how C++ constructs should be used to capture structural and physical implementation concerns. Our explanation relies on the importance of the floorplan and component placement estimations at high levels of ab- straction. We highlight how using object oriented mecha- nisms eases the structural modeling of circuit components, and we present a C++ class library design to specify these structural concerns. 1. Introduction High level modeling using C/C++ models [11] [2] has been proven efficient for architecture exploration and verifi- cation, and the implementability of these models progresses as their productivity gains are demonstrated to engineers and managers. Although complexity is often cited as the primary design concern, building floorplans and layouts is also a challenge since it is difficult to abstract and to predict in a behavioral specification. A design step such as place and route is both hard and time consuming in deep submicron designs [6]. Timing closure is very difficult when a design goes from logical to geometrical granularity, since most of the weight of timing analysis is now a function of the lengths of the in- terconnection between gates rather than by the gates them- selves. These are essentially structural concerns, and the new emerging languages do not have the semantics to capture the information needed to do timing based design[3]. For example, wire lengths and block placements are not cap- tured in functional specification where blocks and wires are not yet necessarily identified or allocated. The connection between C level modeling and physical design is discussed in [8] and in [5]. However, no clear path has yet emerged for the integration of the structural physi- cal information in high level languages. In this paper, we will discuss a semantical approach to specify the structural implementation information in high level models. The im- plementation of the syntax is based on using an object hier- archy to reflect the physical structure of the implementation as a structural object model. We present the Incidence Com- position Structure Project class library to capture layout and floorplanning information in C++ models. 2. Languages and Semantics Many hardware design methodologies and tools with variants of C/C++ or Java have been proposed in the re- cent years. The semantical outlines we can clearly distin- guish for structural composition in the main languages are the following: 1. VHDL and Verilog: formal structural semantic for pro- cess networks and strong connectivity through signals; 2. C: informal semantics, a program is a set of functions with a set of global data structures; 3. C++ and Java: informal semantics, the C functional space augmented with the “object” space where data and functionality is encapsulated. VHDL, Verilog and their variants are well established for RTL design and have yielded many successful designs over the years. Although their synthesizable semantics are