Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm E. Amat, C.G. Almudéver, N. Aymerich, R. Canal, A. Rubio Abstract: 3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that when variability is considered the write access transistor becomes a significant detrimental element on the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some valid strategies in order to mitigate the 3T1D cell variability. Keywords: Variability, DRAM, Temperature 1. Introduction Nowadays, the variability influence on device behavior is well reported as one of main drawbacks for electronic devices in nano- meter regime [1], since it leads to a worsening system behavior. Several types of variability coexist, such as Random Doping Fluctua- tion (RDF), Line Edge Roughness (LER), but RDF has the largest impact on bulk CMOS devices performance [1] as it causes the largest threshold voltage (V T ) fluctuation and consequently supposes a deterioration circuit in behavior. Indeed, memory systems are obviously affected by this varia- bility, and the well established 6T- SRAM cells [2,3] are highly influenced, because a relevant performance lost is manifested in speed reduction and cell instability [3,4]. In this sense, the 3T1D-DRAM is a promising memory cell to substitute it in Very Large System Integration (VLSI) systems. Although, this cell is also affected by the process fluctuations, they do not necessarily impact the operating frequency, unlike 6T [3]. Moreover, 3T1D provides extra benefits: smaller cell area, the non-destructive read process (in contrast to other DRAMs), and large retention time. Thus, the 3T1D-DRAM cell is presented as a suitable memory cell for L1 memory caches [3,5]. In this context, fast access times are required and low retention times are architecturally masked [6]. Note that 3T1D cell is a Dynamic RAM, thus, the memory storage node is a capacitor (the gate capacitance in the gated-diode) and it temporarily stores the data. In order not to lose the contents, a periodic refresh is required to hold data for extended periods [3]. On the other hand, the constant dimension reduction of technologies produces an intolerable increase of leakage current and electric field present in devices. This implies lower carrier mobility and worse reliability [7]. To overcome this problem, the introduction of devices based on high-k dielectrics is a feasible option and it has also allowed a better 3T1D performance beyond 65 nm technology node [2] due to the reduction of the leakage currents. In addition, the introduction of strained channel devices [8] improves carrier mobility. As a consequence, in this work we carry out an analysis of the variability influence on 3T1D cells for technologies beyond 22 nm node. This work is organized as follows. Section 2 describes the cell scheme and its main parameters analyzed during this work. Moreover, different simulation scenarios (variability and tempera- ture) are carried out. Section 3 illustrates the influence of the device variability on 3T1D-DRAM cell. Furthermore, Section 4 reports some strategies to mitigate the memory cell variability. Next, Section 5 pointed out the performance of a 2 kB memory block when it is based on 3T1D-DRAM cells and it is subjected to variability and high environment temperature. Finally, Section 6 discusses the conclusions obtained from this study about the 3T1D performance. 2. Simulation framework The schematic structure for a 3T1D-DRAM memory cell is illustrated in Fig. 1. This cell has been simulated using the 22 nm High Performance Predictive Technology Model (HP PTM) [9]. We have implemented the memory cell using the 2.1 PTM models, which it is based on high-k materials as a gate dielectric and with