ResourceAllocationandBindingApproachforLowLeakagePower ∗ Chandramouli Gopalakrishnan and Srinivas Katkoori Department of Computer Science and Engineering, University of South Florida, Tampa, FL 33620. {cgopalak,katkoori}@csee.usf.edu Abstract We propose a leakage power minimization approach based on Multi-threshold CMOS (MTCMOS) technology. A clique partitioning-based resource allocation and bind- ing algorithm is presented, which maximizes the idle peri- ods of modules in the data-path. Modules with significant idle times are selectively bound to MTCMOS instances. We developeda parameterizableMTCMOS componentlibrary, characterized with respect to sleep transistor width. Us- ingthischaracterization,theleakagepower-delaytrade-off is analyzed and optimal sleep transistor widths are iden- tified. For three well known HLS benchmarks, we ob- tain an average leakage power reduction of 22.44%. The maindisadvantageofMTCMOStechnologyisperformance degradation. We present a performancerecovery technique based on multi-cycling and introduction of slack. With this technique, the performance penalty reduces to as low as 14.28%. We obtain an average leakage power reduc- tion of 17.46% after performance recovery. The average area overhead incurred due to the introduction of MTC- MOS modules is 10.21%. Results are presented for 0.18μm CMOStechnology. 1 IntroductionandRelatedWork As we descend into the deep sub-micron (DSM) regime, static power dissipation due to sub-threshold leakage cur- rent in CMOS VLSI circuits becomes significant. Drastic scaling of V dd in recent years has led designers to reduce threshold voltage to compensate for performance loss. This, however increases the sub-threshold leakage current, which is exponentially related to threshold voltage. This sub-threshold leakage current flows through stacks of OFF transistors. Extensive research on the dependence of leakage current on transistor topology has been done by Chen etal.[1]. At the gate level, Halter and Najm [2] estab- lished that leakage power is statically dependent on the in- puts applied to the gate. One direct way of minimizing leak- age current is to break the path from supply voltage (V dd ) * Work is partially supported by NSF CAREER Award CCR0093301. to the ground (GND). Mutoh [3] proposed a circuit de- sign style called Multi-Threshold CMOS (MTCMOS). The MTCMOS design style is described briefly in Section 2. The authors have fabricated a 1V DSP chip designed using basic MTCMOS cells. The Gated-Vdd technique proposed by Powell et al. [4] is a novel extension to the MTCMOS circuit design style. The authors propose an innovative way to minimize leakage power dissipated in cache memories. There has been more recent work that has been done in leakage power reduction in cache memories with data retention capabilities[5] and low performance overhead [6]. Khouri et al. [7] bind in- stances to a module library consisting of high V T and low V T components. The authors bind operations on the criti- cal path to high V T instances to maintain performance. A comprehensive survey of leakage minimization techniques is provided by Roy[8]. In this work, we propose a resource allocation and bind- ing approach for low leakage power. Resources are allo- cated in a way such that they are idle for maximum contigu- ous time periods. Resources with significant idle periods are bound to MTCMOS modules. We present an MTCMOS module library characterized for leakage power and delay. To alleviate the performance loss due to MTCMOS mod- ules, we propose a performance recovery technique based on multi-cycling and introduction of slack. The techniques proposed in this work have been incorporated into AUDI, a high level synthesis (HLS) system currently being devel- oped by the authors. Leakage power management tech- niques are already incorporated into the system [9]. Results are presented for three well known datapath intensive de- signs. The rest of the paper is organized as follows. Section 2 presents a MTCMOS component library characterized for leakage power and delay. Section 3 proposes a resource al- location and binding algorithm for low leakage power. Sec- tion 4 introduces a performance recovery technique based on multi-cycling and introducing slack. Section 6 reports the experimental results. Section 7 concludes the paper with a summary. Proceedings of the 16th International Conference on VLSI Design (VLSI’03) 1063-9667/03 $17.00 © 2003 IEEE