A Modeling Methodology and Pre-Run-Time Scheduling for Embedded Real-Time Software Raimundo Barreto * Depto de Ciˆ encia da Computac ¸˜ ao (DCC) Universidade Federal do Amazonas (UFAM) Av. Rodrigo Ramos 3000 Aleixo, 69077-000 Manaus-AM-Brazil rsb@cin.ufpe.br Paulo Maciel S´ ergio Cavalcante Centro de Inform´ atica (CIn) Universidade Federal de Pernambuco (UFPE) PO Box 7851, 50732-970, Recife-PE-Brazil {prmm, svc}@cin.ufpe.br Abstract One of the most intricate problem in the synthesis of real- time systems is the scheduling. This paper presents a for- mal modeling methodology based on time Petri nets (TPN) and a framework for application-specific scheduler synthe- sis. Finding a feasible scheduling is not an easy task be- cause this problem, in its general form, is NP-hard. The method proposed in this paper finds a scheduling, whether one exists, using state space exploration. The problem with this approach is the space size, which can be very large for medium to large systems. This paper shows how to minimize this problem using behavior restrictions at system model- ing, and a partial-order reduction method. Additionally, the algorithm proposed for finding a feasible schedule uses a depth-first search based method. Therefore, states are only generated if strictly necessary. It is verified through real- world experimental results that a schedule is found examin- ing a reduced number of states . 1. Introduction Embedded real-time systems are dedicated applications, which is embedded in a larger environment, having to sat- isfy stringent timing constraints. One of the most intricate problem in the synthesis of these systems is the schedul- ing. The scheduler is responsible for task execution or- der on processors. Generally, a scheduler is constructed from a given well-known scheduling policy that orders the tasks’ execution, where this ordering is called schedule. The scheduler synthesis proposed in this work considers a differ- ent approach since the scheduling policy is not known in ad- vance, but it entirely depends on the specification. An essen- * PhD Student at CIN/UFPE tial activity in real-time systems schedulers is the schedula- bility analysis, in which the process of verifying whether the timing constraints are violated are carried out. The schedul- ing algorithm is a pre-run-time scheduling, i.e., it is per- formed at design time, which can achieve 100% processor utilization and excludes the need for complex operating sys- tem. Therefore, it is guaranteed that, if a schedule is found all timing constraints are met. The proposed method accom- plishes the schedulability analysis and the scheduler synthe- sis simultaneously. However, finding a valid schedule is not a trivial task, as this problem, in its general form, is NP- hard. This work uses state space exploration because it is a simple, easy and fully automatic strategy for analyzing and verifying finite-state systems [8]. It consists in checking all successor states recursively, starting at a given initial state, by executing all enabled transitions in each state. In spite of scheduling can be determined by exploration, this solu- tion is limited by excessive size of its state space. This prob- lem comes up due to the interleaving of concurrent events. For instance, the analysis of n concurrent events explores all n! traces. This exponential growth is known as the state ex- plosion problem. In this paper it is shown how to minimize this problem using behavior restrictions at system modeling, and partial- order reduction methods. Additionally, the approach uses a depth-first search method for finding a feasible schedule. Hence, states are only generated if strictly necessary. Thus, generally the schedule is found examining just a small num- ber of states as it can be seen in the experimental results. The proposed real-time specification can include a set of non-preemptable tasks with bounded discrete time values, priorities, deadlines, release times, periodic and sporadic ar- rival, precedence and mutual exclusion relations, and any fi- nite number of resources, including processors, buffers, and any shared data variables. The method translates the spec- ification to time Petri net (TPN) formalism, where the se- Proceedings of the 15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD’03) 0-7695-2046-4/03 $17.00 © 2003 IEEE