IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 3, MARCH 2012 777 A Compact Analytic Model of the Strain Field Induced by Through Silicon Vias Sun-Rong Jan, Tien-Pei Chou, Che-Yu Yeh, Chee Wee Liu, Senior Member, IEEE, Robert V. Goldstein, Valentin A. Gorodtsov, and Pavel S. Shushpannikov Abstract—The thermoelastic strains are induced by through silicon vias due to the difference of thermal expansion coefficients between the copper (∼18 ppm/ ◦ C) and silicon (∼2.8 ppm/ ◦ C) when the structures are exposed to a thermal ramp in the process flow. A compact analytic model (Bessel function) of the strain field is obtained using Kane–Mindlin theory, and has a good agreement with the finite-element simulations. The elastic strains in the silicon in the radial direction and angular direction are tensile and compressive, respectively. The linear superposition of the analytic model of a single via can be used in the multi-via configuration. Due to the interaction of vias, the slightly larger errors of strain occur between the two close vias when the linear superposition is used. Index Terms—Compact modeling, strain field, through silicon via (TSV). I. I NTRODUCTION D EVICE scaling beyond the 22-nm node encounters physical constraints and technological challenge. Three- dimensional ICs [1]–[4] can increase the device density along the third dimension, whereas the conventional device scaling hits the red brick wall. The stacking of ICs with the through sil- icon vias (TSVs) has been a crucial technology for the vertical interconnections, resulting in the enhanced circuit performance and the shrinkage of the system size. Since the filling materials of TSVs and silicon have dif- ferent coefficients of thermal expansion (CTE), cooling from the process temperature to device operation temperature leads to the strain field around TSV. The thermoelastic strains in- Manuscript received October 4, 2011; revised December 2, 2011; accepted December 8, 2011. Date of publication January 24, 2012; date of current version February 23, 2012. This work was supported in part by the National Science Council of Taiwan under Grant 95-2218-E-002-065-MY3 and in part by the Russian Foundation for Basic Research under Grant 09-01-92004. The review of this paper was arranged by Editor R. Venkatasubramanian. S.-R. Jan is with the Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan. T.-P. Chou and C.-Y. Yeh are with the Department of Electrical Engineering and Graduate Institute of Photonics and Optoelectronics, National Taiwan University, Taipei 106, Taiwan. C. W. Liu is with the Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan, and also with the Department of Electrical Engineering and Graduate Institute of Photonics and Optoelectronics, National Taiwan University, Taipei 106, Taiwan (e-mail: chee@cc.ee.ntu.edu.tw). R. V. Goldstein, V. A. Gorodtsov, and P. S. Shushpannikov are with the A.Yu. Ishlinsky Institute for Problems in Mechanics, Russian Academy of Sciences, 119526 Moscow, Russia. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2011.2180534 Fig. 1. (a) Structure and the material parameters of the TSV filler (Cu), the insulating layer (SiO 2 ), and the wafer (Si). (b) The dent (3-D effect) on the TSV surface. troduced by TSVs in the active area [5], [6] can affect the carrier mobility [7]. The strain effect induced by TSV should be formulated and taken into consideration for chip design. The proper strain field can further enhance the performance, whereas a keep-out zone (KOZ) [1], [4] should be known in advance for the purpose of minimizing variability in devices. The CTE of the copper filler (∼18 ppm/ ◦ C) [8] is much larger than that of the silicon (∼2.8 ppm/ ◦ C). The thermal ramp from the process temperature of 200 ◦ C [6] to the room temperature causes the strain field. Experimentally, the spatial and mag- nitude resolution of strain measured by Raman measurement [9], [10] are only 1–4 μm and ∼50 MPa, respectively [10]. The analytic modeling is of particular importance to know the details of the strain distribution for 3-D IC design. To solve the problem on the strain field distribution analyt- ically, previous work [6] uses the simple isotropic 2-D Lame solution without taking the liner (SiO 2 ) into consideration and causes error in the vicinity of TSV. Our proposed TSV model (Bessel function) is based on the quasi-3-D Kane–Mindlin theory with SiO 2 liners and has better accuracy in the vicinity of TSV. II. DESCRIPTION OF THE MODEL The linear elastic body considered in the analytic model consists of the TSV filler (Cu, labeled as V), an insulating layer (SiO 2 , labeled as I), and a wafer (Si, labeled as W) [see Fig. 1(a)]. The Cu filler is in 0 <r<R 1 (= 3 μm), SiO 2 is in R 1 <r<R 2 (= 3.3 μm), and Si is in R 2 <r<R Si . Note 0018-9383/$31.00 © 2012 IEEE