International Journal of Computer Applications (0975 – 8887) International Conference on Communication, Circuits and Systems “iC3S-2012” 26 Analytical Drain Current Model for Symmetrical Gate Underlap DGMOSFET Sudhansu Kumar Pati Hemant Pardeshi Godwin Raj Chandan Kumar Sarkar Nano Device Simulation Laboratory, Department of Electronics & Telecommunication Engineering, Jadavpur University, Kolkata - 700 032, India Arghyadeep Sarkar Department of Electronics & Communication Engineering Meghnad Saha Institute of Technology, Uchhepota, Kolkata 700 150 N Mohan Kumar SKP college of Engineering, Tiruvannamalai, Tamilnadu - 606 611, India ABSTRACT The drain current model of symmetrical Underlap DGMOSFET is evaluated for subthreshold region. Model data is verified with simulation data for validation of the proposed model. For validation the drain current is evaluated with respect to gate to source potential. The drain current is calculated with variation of gate length, underlap length and silicon body thickness. As the gate length and underlap length increases, the drain current decreases and as silicon body thickness increases, increase of drain current is observed. General Terms Semiconductor Devices, MOSFET Modelling. Keywords Drain current, Ultrathin body, Virtual source, Underlap DGMOSFET 1. INTRODUCTION DOUBLE GATE (DG) MOSFET is a candidate which reduces short channel effects (SCEs) and gives better scalability and performances [1].The DG MOSFET has been made known very good electrostatic gate control over the channel, permitting gate length scaling down to 10 nm [2].Gate underlap of source/drain has a vital importance over lightly or undoped channel double-gate MOSFETs [3,4]. Gate underlap or non-overlap has more advantages over double- gate MOSFETs in subthreshold region such as it reduces gate edge direct tunneling leakage, gate sidewall fringe capacitance and also reduces SCE due to increase in effective channel length, ensuring improved circuit performance. Gate underlap DGMOSFET can be used in subthreshold circuit for ultra-low power consumption with low to medium frequency [5]. The current modeling of gate underlap DGMOSFET is necessary to know the drive capability of the transistor. Asymmetrical gate underlap modeling was given by[6], still symmetrical current modeling is to be investigated for subthreshold regime. Underlap DG devices functioned at small current intensities are predominantly suitable for ULV analog/RF applications as gain and speed of devices can be considerably enriched [7]. 2. THE SUBTHRESHOLD CURRENT MODEL For weak inversion region, the 2D Poisson’s equation of gate underlap DGMOSFET (as shown in Fig.1) for three regions (I, II and III) are given by 2 2 2 2 (, ) (, ) (1) i i a Si xy xy qN x y        Where Ψ i (x, y) is the potential variation in three regions (for i=I, II and III) along x and y direction, q is the electronic charge, N a is doping concentration along the channel and ε Si is permittivity of silicon. Fig.1 interprets the separation of the three regions. The potentials of three regions are considered as parabolic is given by [6, 8] 2 1 2 3 (, ) () () () (2) i i i i xy x xy xy     1 () i x  , 2 () i x  and 3 () i x  are the coefficients to be evaluated by proper boundary conditions. Since inner fringing field from the gate side wall affect the current conduction, to avoid tough mathematical burden we considered a minimum surface potential model i.e. virtual source. The surface potential model was derived [8] for three regions. We investigated the minimum surface potential occur at region-II (Gate overlap region).The surface potential of region –II is given by [8] 2 2 ( ) ( ) (, ) (3) a s gs ms si xL xL un un qN xy Ce De V              where L un is underlap length, V gs is gate to source potential ,ɸ ms is difference of work function between metal and semiconductor, the coefficient C and D can be calculated from[8] and natural length λ is given by 1 2 4 si ox si ox si ox si ox tt t t             , Where t si and t ox is thickness of body and oxide and є ox is oxide permittivity. The minimum surface potential point x can be calculated from 2 (, ) 0 s xy x    , Substituting the value of x in (3) we have minimum surface potential