32 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 4, NO. 1, MARCH 2004
Effect of P/E Cycling on Drain Disturb in Flash
EEPROMs Under CHE and CHISEL Operation
Deleep R. Nair, Student Member, IEEE, Nihar R. Mohapatra, Member, IEEE, Souvik Mahapatra, Member, IEEE,
Shoji Shukuri, and Jeff D. Bude, Associate Member, IEEE
Abstract—Drain disturb is studied in NOR flash EEPROM
cells under CHE and CHISEL programming operation, before
and after repeated program/erase (P/E) cycling. Drain disturb is
shown to originate from band-to-band tunneling under CHISEL
operation, unlike under CHE operation where it originates
from source-drain leakage. Under identical initial programming
time, CHISEL operation always shows slightly lower program/
disturb (P/D) margin before cycling but similar P/D margin after
repetitive P/E cycling when compared to CHE operation. The
degradation of gate coupling coefficient that affects source/drain
leakage and the increase in trap-assisted band-to-band tunneling
seems to explain well the behavior of CHE and CHISEL drain
disturb after cycling.
Index Terms—Band-to-band tunneling, CHE, CHISEL, cycling
endurance, drain disturb, flash EEPROM.
I. INTRODUCTION
N
OR FLASH EEPROM cells are programmed either by
channel hot electron (CHE) [1] or by CHannel Initiated
Secondary ELectron (CHISEL) [2]–[14] injection mechanisms.
CHE injection involves injection of lateral field heated
channel electrons into the floating gate (FG). Note that the CHE
process does not rely on impact ionization. On the other hand,
CHISEL injection relies on impact ionization feedback and is
activated by the application of a negative substrate bias
that results in a high transverse field near the drain
junction. This causes high-energy electron injection into the FG
over a spatially broad area in the channel. The schematic of CHE
and CHISEL injection is shown in Fig. 1.
Compared to the CHE process, CHISEL injection provides
faster programming time under equivalent programming
power and lower voltage and lower power operation for equiva-
lent . CHISEL injection also offers self-convergent program-
ming leading to excellent threshold voltage control and a
unique recovery procedure for over erased cells not available
under conventional CHE programming [2]–[13]. CHISEL pro-
gramming also shows better program/erase (P/E) cycling en-
durance of window and lower degradation compared to
CHE operation [14], [15]. Most of the studies done so far were
Manuscript received September 11, 2003; revised November 13, 2003. The
work of D. R. Nair was supported in part by Siemens AG.
D. R. Nair, N. R. Mohapatra, and S. Mahapatra are with the Department of
Electrical Engineering, Indian Institute of Technology Bombay, India (e-mail:
drnair@ee.iitb.ac.in; nihar@ ee.iitb.ac.in; souvik@ee.iitb.ac.in).
S. Shukuri is with the Semiconductors and Integrated Circuits Group, Hitachi
Ltd., Japan (e-mail: shoji-shukuri@sic. hitachi.co.jp).
J. D. Bude is with Agere Systems, Allentown, PA 18109 USA (e-mail:
bude@agere.com).
Digital Object Identifier 10.1109/TDMR.2004.824371
Fig. 1. Schematic of CHE (top) and CHISEL (bottom) injection mechanisms.
Filled and open circles represent electrons and holes, respectively. Impact
ionization is present during CHE operation (not shown), but does not contribute
to the injection process.
Fig. 2. Schematic of a NOR flash memory array showing cells under program
(Cell A) and drain disturb (Cell B) condition.
concentrated on the effect of P/E cycling on the CHE/CHISEL
programming performance of memory cells.
Drain disturb (during programming) is an important relia-
bility issue for NOR flash EEPROMs [16], [17]. It causes
shift in cells that have unselected wordline (WL) but share the
same bitline (BL) of a cell being programmed, as shown in
Fig. 2. The application of during CHISEL operation results
in a larger across the drain junction, which can aggra-
vate drain disturb. Furthermore, drain disturb can worsen after
P/E cycling and, therefore, requires careful attention. This paper
1530-4388/04$20.00 © 2004 IEEE
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