978 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 9, SEPTEMBER 2004 A Behavioral Synthesis System for Asynchronous Circuits Matthew Sacker, Andrew D. Brown, Senior Member, IEEE, Andrew J. Rushton, and Peter R. Wilson, Member, IEEE Abstract—Behavioral synthesis of synchronous systems is a well established and researched area. The transformation of behavioral description into a datapath and control graph, and hence, to a structural realization usually requires three fundamental steps: 1) scheduling (the mapping of behavioral operations onto time slots); 2) allocation (the mapping of the behavioral operations onto abstract functional units); and 3) binding (the mapping of the functional units onto physical cells). Optimization is usually achieved by intelligent manipulation of these three steps in some way. Key to the operation of such a system is the (automatically generated) control graph, which is effectively a complex sequence generator controlling the passage of data through the system in time to some synchronizing clock. The maximum clock speed is dictated by the slowest time slot. (This is the timeslot containing the longest combinational logic delay.) Timeslots containing quicker (less) logic will effectively waste time: the output of the combinational logic in the state will have settled long before the registers reading the data are enabled. If we allow the state to change as soon as the data is ready, by introducing the concepts of “ready” and “acknowledge,” the control graph becomes a disjoint set of single-state machines—it effectively disappears, with the consequence that the timeslot–timeslot transitions become self controlling. Having removed the necessity for the timeslots to be of equal duration the system becomes selftiming: asynchronous. This paper describes a behavioral asynchronous synthesis system based on this concept that takes as input an algorithmic description of a design and produces an asynchronous structural implementation. Several example systems are synthesized both synchronously and asynchronously (with no modification to the high level de- scription). In keeping with the well-established observation that asynchronous systems operate at average case time complexity rather than worse case, the asynchronous structures usually operate some 30% faster than their synchronous counterparts, although interesting counterexamples are observed. Index Terms—Asynchronous synthesis, behavioral synthesis. I. INTRODUCTION A SYNCHRONOUS circuits have many potential ad- vantages over their synchronous equivalents [1]–[3], including lower latency, lower power consumption, and lower electromagnetic interference. However, their acceptance into industry has been slow, which may be due to a number of reasons: First, the techniques required to design synchronous circuits are well known and taught to all students of electronics, whereas few people have the skills to design asynchronous Manuscript received March 27, 2003; revised August 19, 2003. This work was supported by the Royal Society and the Engineering and Physical Science Research Council (EPSRC), U.K. The authors are with the University of Southampton, Hampshire SO17 1BJ, U.K. (e-mail: ms00r@ecs.soton.ac.uk; adb@ecs.soton.ac.uk; ajr1@ecs.soton.ac.uk; prw@ecs.soton.ac.uk). Digital Object Identifier 10.1109/TVLSI.2004.832944 circuits. Second, few tools are available outside of the aca- demic community to aid the design of asynchronous circuits, compared to the large number of commercial tools available for the design of synchronous circuits. To address both these problems an asynchronous behavioral synthesis tool has been created that supports the implementation of large asynchronous designs without the need to understand the architectures of the circuit produced. Behavioral synthesis allows circuits with different architec- tures to be quickly realized from a single specification. Trade- offs between parameters such as area and delay can be used to explore different points within the design space, while the tech- nology independent specification allows the design to be tar- geted at different technologies. The MOODS [4]–[7] synthesis system is an advanced tool for synthesizing synchronous cir- cuits. It has now been extended to allow both synchronous and asynchronous circuits to be synthesized from a single behavioral description, with no change to the design definition. Behavioral synthesis is the process of transforming an algo- rithmic specification into a physical architecture (“Algorithms to Silicon”). This is a well studied problem [8], [9], and many techniques have been developed [10]–[12] to attack it. As with asynchronous technology, behavioral synthesis has yet to pen- etrate deeply into the design community. Design teams under- standably exhibit high inertia, a new technology is not readily accepted until someone else has used it extensively. Asynchronous circuits can be designed at various levels of abstraction, from manual design, to the synthesis of low-level asynchronous state machines, through data transfer level (DTL) specification and onto behavioral synthesis. As for synchronous circuits, asynchronous circuits can also be designed by hand. The AMULET [13]–[15] processors are a good example of the use of asynchronous circuits, based on micropipelines [16], designed by hand to be ARM compatible and have comparable performance. The synthesis of asynchronous controllers has been an area of considerable research. The two most notable techniques are the synthesis of Petri-net.[17] specifications using Petrify [18], and the synthesis of burst mode state machines using minimalist [19] or three-dimensional (3-D) [20], [21]. Although these sys- tems have different input specification style, they all create asyn- chronous state machines from two-level hazard free logic. Stepping up from small asynchronous state machines, there are several synthesis tools that operate at the DTL, equivalent to the register transfer level (RTL) of synchronous design. Balsa [22], [23] and Tangram, [24] both use similar input languages based on CSP [25] and OCCAM [26], and generate circuits using the handshake circuit methodology. These tools have been 1063-8210/04$20.00 © 2004 IEEE