Watermarking strategies for IP protection of micro-processor cores L. Parrilla a , E. Castillo a , U. Meyer-Baese b , A. García a , D. González a , E. Todorovich c , E. Boemo c , A. Lloris a a Dept. of Electronics and Computer Technology, Campus Universitario Fuentenueva, 18071, Univ. of Granada, Spain. b Dept. of Electrical & Computer Engineering, FAMU-FSU College of Engineering, Florida, USA 32310-6046. c School of Engineering, Universidad Autónoma de Madrid, 28049, Madrid, Spain. ABSTRACT Reuse-based design has emerged as one of the most important methodologies for integrated circuit design, with reusable Intellectual Property (IP) cores enabling the optimization of company resources due to reduced development time and costs. This is of special interest in the Field-Programmable Logic (FPL) domain, which mainly relies on automatic synthesis tools. However, this design methodology has brought to light the intellectual property protection (IPP) of those modules, with most forms of protection in the EDA industry being difficult to translate to this domain. However, IP core watermarking has emerged as a tool for IP core protection. Although watermarks may be inserted at different levels of the design flow, watermarking Hardware Description Language (HDL) descriptions has been proved to be a robust and secure option. In this paper, a new framework for the protection of μP cores is presented. The protection scheme is derived from the IPP@HDL procedure and it has been adapted to the singularities of μP cores, overcoming the problems for the digital signature extraction in such systems. Additionally, the feature of hardware activation has been introduced, allowing the distribution of μP cores in a “demo” mode and a later activation that can be easily performed by the customer executing a simple program. Application examples show that the additional hardware introduced for protection and/or activation has no effect over the performance, and showing an assumable area increase. Keywords: Microprocessor, IP Cores, Intellectual Property Protection, FPGAs, Hardware Activation. 1. INTRODUCTION The new design strategies based in the reuse of IP-cores 1 enables the optimization of company resources due to reduced development time and costs, especially when implementing highly complex systems. This is of special interest in the Field-Programmable Logic (FPL) domain. However, this design methodology introduces risks concerning the intellectual property protection (IPP) of those cores, with most forms of protection in the EDA industry being difficult to translate to this domain. Nowadays, IP core watermarking 2,3,4 has emerged as a tool for IP core protection. Although watermarks may be inserted at different levels of the design flow, watermarking Hardware Description Language (HDL) descriptions 5,6 has been proved to be a robust and secure option. The embedding of a watermark at this design level provides the most tampering resistant schemes since the signature is embedded in preliminary stages, and it is dragged through the whole design flow 6 . In this sense, IPP@HDL 6 procedure provides a protection framework for IP cores by spreading a digital signature at the HDL design level through memory structures or combinational logic included in the design. In this design environment, microprocessor and microcontroller cores are widely used and are, in most cases, the basis to implement complex systems. The protection of these cores has become a priority for the developers. Although IPP@HDL can be applied directly to protect microprocessor (µP) based designs, some issues related to extracting the digital signature must be considered: - In µP-based systems, the data bus is not always part of the I/O connections and it can be difficult to introduce the sequence to initiate the watermark extraction. The RESET pin can be an option to overcome this drawback. Independent Component Analyses, Wavelets, Neural Networks, Biosystems, and Nanoengineering VIII, edited by Harold H. Szu, F. Jack Agee, Proc. of SPIE Vol. 7703, 77030L · © 2010 SPIE · CCC code: 0277-786X/10/$18 · doi: 10.1117/12.850526 Proc. of SPIE Vol. 7703 77030L-1 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/22/2015 Terms of Use: http://spiedl.org/terms