Analysis of transition region and accumulation layer eect in the subthreshold slope in SOI nMOSFETs and their in¯uences on the interface trap density extraction Victor Sonnenberg a, b, *, JoaÄo Antonio Martino a a LSI Ð Laborato Ârio de Sistemas Integra Âveis Ð Escola PoliteÂcnica da Universidade de Sa Äo Paulo, Av. Prof. Luciano Gualberto, 158 trav.3 Ð CEP 05508-900 Sa Äo Paulo, Brazil b MPCE Ð Faculdade de Tecnologia de Sa Äo Paulo Ð FATEC/SP, Pc ° a Cel. Fernando Prestes, 30 Ð CEP 01124-060 Sa Äo Paulo, Brazil Received 7 June 1999; received in revised form 3 July 1999; accepted 13 July 1999 Abstract Measurements were performed in thin ®lm silicon on insulator (SOI) nMOSFETs and it was observed a transition region in the subthreshold slope, larger than the theoretically expected, when the back interface (silicon ®lm/buried oxide) changes from accumulation to depletion. Also, it was observed a non-constant plateau in the subthreshold slope when the back interface is accumulated. MEDICI numerical bidimensional simulations were performed in order to analyze this transition region. It was veri®ed that there is a back gate voltage range where a part of the back interface is not depleted over the whole subthreshold region, depending on the front gate voltage, which in¯uences strongly the determination of the subthreshold slope, resulting in a non-abrupt transient region. It is proposed a method for extracting the interface trap density in gate oxide/silicon ®lm and silicon ®lm/buried oxide interfaces minimizing the in¯uence of the back accumulation layer in the subthreshold slope with the back interface accumulated. This method was also applied experimentally. # 1999 Elsevier Science Ltd. All rights reserved. 1. Introduction The subthreshold slope is an important parameter for the MOSFETs devices mainly in low voltage and low power operation [1]. The silicon on insulator (SOI) MOSFETs have pre- sented many advantages over bulk MOSFETs as improved subthreshold slope, small radiation eect and suppression of the latch-up in CMOS technology [2]. The SOI nMOSFET cross-section is shown in the Fig. 1. Thin ®lm fully depleted SOI MOSFET presents a good subthreshold slope near the theoretical lower limit, around 60 mV/dec at room temperature. If the back gate voltage is applied to accumulate the back interface, the subthreshold slope increases for a value above than the bulk MOSFET one [2]. The values of the subthreshold slope with the back interface depleted and accumulated are, normally, used for obtaining process parameters such as interface trap density (N it ) [3±5]. Solid-State Electronics 43 (1999) 2191±2199 0038-1101/99/$ - see front matter # 1999 Elsevier Science Ltd. All rights reserved. PII: S0038-1101(99)00191-4 * Corresponding author. Tel.: +55-11-818-5657; fax: +55- 11-818-5665. E-mail address: sonnen@lsi.usp.br (V. Sonnenberg)