THE EFFECT OF BARRIER SURFACE OXIDES ON ALGAN/GAN HEMT RELIABILITY M. Ťapajna a , N. Killat a , U. Chowdhury b , J. L. Jimenez b , and M. Kuball a,* a Center for Device Thermography and Reliability (CDTR), H.H. Wills Physics Laboratory, University of Bristol, Tyndall Avenue, Bristol BS8 1TL, UK b TriQuint Semiconductor, 500 West Renner Road; Richardson, TX 13440, USA * E-mail: martin.kuball@bristol.ac.uk, Phone: +44 117 928 8734, Fax: +44 117 925 5624 Abstract In this work, we show that HEMTs processed with cleaning steps leading to surface oxides formation are more susceptible to degradation in terms of gate leakage and trapping characteristics, although these oxides seem to passivate surface traps in fresh state. This indicates that oxygen related trap states may play a crucial role for AlGaN/GaN HEMT reliability. I. Introduction AlGaN/GaN HEMTs are able to handle unprecedented RF power making them the most prominent candidate for radar and satellite applications, however, their reliability still offers opportunities for improvement [1- 3]. It has been shown that different types of cleaning prior to nitride passivation and gate formation have a strong impact on the gate breakdown voltage [4]. In this work, reliability of production-quality AlGaN/GaN HEMTs with two different surface treatments was systematically studied using a novel electrical-optical methodology developed in [5]. II. Experimental details GaN/AlGaN/GaN HEMTs grown by MOCVD on SiC substrate were fabricated using standard III–V processing technology. Prior to passivation layer deposition, the samples received different cleaning treatments using chemicals with different levels of oxygen content referred to as cleaning A and B in the following. X-ray photoelectron spectroscopy and Auger electron spectroscopy analysis showed a surface oxygen content of about 20% and 30% for samples with cleaning A and B, respectively, indicating a more pronounced surface oxidation of the GaN cap layer for the latter. Devices with 400 μm total gate periphery were stressed in off-state condition at V ds =30 V, V gs =- 5 V and base plate temperatures (T b ) 25, 100, 150, and 200 °C. Electrical characteristics in DC and pulsed mode together with trapping characteristics similar to [5] were measured. Electroluminescence (EL) imaging was employed to gain insight into the changes in lateral electric field distribution upon stressing. III. Results and discussion In fresh state, the Schottky gate contact of HEMTs after cleaning A and B shows a forward voltage of about 0.6 V and 1.3 V, respectively, while both HEMTs revealed a similar threshold voltage (from -3.65 to - 3.45 V). This indicates the presence of an extra tunneling barrier between the semiconductor and the gate for devices after cleaning B. Fig. 1 shows the evolution of the HEMTs gate current (I g ) during stress performed at different T b . Although HEMTs after cleaning B show four orders of magnitude lower I g than for after A and small gate-lag (Fig. 2) in a fresh state, both parameters progressively degrade for B and eventually approach about the same values as measured on HEMTs with cleaning A after off-state stress performed at higher than T b =150 °C. In contrast, devices A show relatively high I g and gate-lag, however, these parameters remain stable upon off-state stress regardless of T b . 0 10 20 30 40 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 0 10 20 30 40 Cleaning A T b =22°C T b =100°C T b =150°C T b =200°C I g (A) Stress time (h) Stress time (h) Cleaning B Fig. 1 Evolution of the gate leakage current (V gs =-7 V and V ds =10 V) measured before (t=0), during, and one day after (t=42 h) off-state stress as a function of T b for HEMTs with different surface treatment.